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Coding Styles for Improved QOR

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RTL coding style plays an important role for getting optimal results. Synthesis tools support specifi c coding templates for inferring different primitives. Modern tools understand and map to the desired primitives when the user codes in a slightly dif- ferent way and maintains the intent, but for getting repeatable results, follow the usually recommended coding practices. Below are few specifi c suggestions: 

• Avoid using too many hierarchies. Else different fl attening options will provide signifi cantly different results. 

• A simple code using simple constructs is always better. It helps in understanding the intent if you have to revisit the code after a while. Plus, however smart a tool might be, a simpler code would give you the best result always. For example, instead of using a for-loop to assign individual bits, assign the whole bus. 

• Look for cases where the tool might do resource sharing. If you need perfor- mance, code using parallel structures. 

• Avoid instantiation in RTL unless really required. Synthesis tools would not opti- mize an instantiated primitive. 

• Constrain the ranges if the signals/parameters do not need full range evaluation. For example, signals in vhdl if declared as integer type should be constrained as 0–15 , if you need only 16 values. 

• Avoid logic functionality while port mapping. A simple example below illustrates the importance of coding style: 

module top (

                input [3:0] din,

                output dout

                 );

sub u (

                 .din(din[3:2] | din[1:0]),

                 .dout(dout)

                  );

endmodule

module sub (

                  input [1:0] din,

                  output dout

                   );

assign dout = &din;

endmodule

In the above example, the output is just a function of four inputs. Synthesizing this one would expect one LUT4 and one logic level. But this may not happen always. Consider a DONT_TOUCH on sub or this design is run with fl atten_hierarchy none option. In that case, there would be two LUTs and two logic levels. The point to note here is that coding logic during port mapping can be an easy option for making quick code changes but the repercussions due to the same should be thought up-front.

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