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Synthesis tools support directives/attributes which can be used in RTL and or XDC to provide fi ner control to the user. These can be used to change default mapping by synthesis and stop/force some optimizations.
Though a tool could support lot of attributes to control the behavior, an important point to be noted is the implication of these attributes when used in different con- texts. Let us look at few examples which illustrate this.
Below is a simple RTL which has max_fanout applied on the enable signal which drives 1024 fl ops:
module top (
….
output reg [1023:0] dout
);
(* max_fanout = 10 *) reg en_r;
always @ (posedge clk)
…
if(en_r)
dout <= din;
Consider the scenario when the attribute is not used. This RTL will infer 1025 flip-flops, which would be placed in 65 slices (assuming 16 fl ops being packed per slice ). All the 1024 registers have the same control signal.
Now let us consider the case where max_fanout of 10 is used. Synthesis will replicate en_r 1024/10 (103) times. So we have 103 control sets now. This will use 103 slices for 1024 registers. Due to replication we have 103 additional fl ops which need ~seven slices.
In the above example, though your intention was to reduce the fanout for improved timing, you can see that control sets played a role which ended up in a considerable area overhead.
Let us look at another example of how multiple attributes when used in conjunc- tion can become nondeterministic. Consider a case where you have an FSM and want to force the encoding to one-hot and want to debug this using logic analyzer . To achieve this, fsm_encoding attribute along with mark_debug would be applied.
At a fi rst glance, it looks correct. But there is a confl ict. mark_debug implies that the exact signal name be intact. With fsm_encoding as one-hot, there would be addi- tional fl ops and state name would get changed. So synthesis tool chooses to honor mark_debug and fsmencoding would be ignored. A better way in this case would be to add mark_debug post-synthesis via XDC so that the encoded FSM state would be available for debug.
Look at synthesis log fi le for any message related to attribute being ignored for some reason. DONT_TOUCH stops optimizations in the complete fl ow. So make sure that it is intended.
XDC provides a powerful mechanism which can be used to apply attributes with- out having the need to change the RTL. Consider a simple example of a module which describes the memory being instantiated in different hierarchies. If you want to map few hierarchies to block RAM and few hierarchies to distributed RAM , a simple Tcl-based XDC can be used, as shown:
set_property RAM_STYLE distributed [get_cells u/u1]
set_property RAM_STYLE block [get_cells u/u2]
Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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