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Each register or latch in any FPGA device can be individually confi gured to power up in a known 0 or 1 state. This initial state is independent of any asynchronous clear or preset signals used to operate the register. The INIT attribute defi nes the initial power-up state of registers and latches. An initialization in HDL will cause Vivado synthesis tool to attach the corresponding INIT. The initialization given below will result in register with INIT value as 1 :
reg state_bit = 1;
In ASIC world, there is no such provision. This would imply that while you need to specifi cally have a reset or set in an ASIC, for FPGAs, you should just initialize your registers and can get rid of set/reset conditions for the fl ops and latches.
FPGAs have dedicated memory blocks (distributed/block RAM). These support ini tial values which can be used for applications like ROM on power up. Synthesis tools support inferring these initializations when coded using initial blocks and using $readmemh/$readmemb to initialize memories:
reg [31:0] mem [1023:0] ;
initial begin
$readmemb("init.dat", mem) ;
end
For an ASIC, there is not much difference (in timing) between an adder followed by MUX and MUX followed by an adder which performs the same functionality. But FPGA architectures have CARRY chains which are preceded by LUTs. In this con-
text, consider two scenarios:
• An adder followed by a MUX
• MUX followed by an adder
Fig. 9.1 RTL view before MUX pushing
Fig. 9.2 RTL view after MUX pushing
The fi rst one results in 1 additional LUT + 1 logic level. The second one can combine the adder into the same LUT. The RTL code segment below would result in an adder followed by a MUX, as shown in the schematic of Fig. 9.1 :
always @ (posedge clk)
begin
…
if(sel_reg)
dout <= din_reg + din0_reg;
else
dout <= din_reg + din1_reg;
end
The critical path in Fig. 9.1 is through the adder and the MUX. This is translated to 1 LUT + 2 CARRY4 + 1 LUT. The same functionality can be recoded as below to give a circuit as shown in Fig. 9.2 , where MUX is moved in front of the adder:
always @ (posedge clk)
begin
…;
dout <= din_reg + dout_tmp;
end
dout_tmp = sel_reg ? din0_reg: din1_reg;
One-bit addition and the MUX can now be combined into the same LUT. So the critical path is now 1 LUT + 2 CARRY4 .
Clock gating is a popularly used technique in ASICs and FPGAs for eliminating unnecessary switching activity there by reducing dynamic power . Based on the design functionality, designers will add this gating logic to drive sequential elements which will disable clock as and when required.
Since clocking resources on an FPGA are predetermined, gating might have to be done within the specifi c clocking structures available. A gating logic on clock path for an FPGA could result in skew and thereby timing violations , especially hold violations.
You can move the gating logic onto clock buffer as shown in Fig. 9.3, specially if the same gated clock controls a high number of elements. These clock buffers are designed to prevent spurious clocking, due to change in enable while the clock is in active phase.
Gating logic on clock path should typically be moved to enable path for fl ip-fl ops or latches. Vivado synthesis tool will do this automatically (under user option). But if the structures are too complicated, user intervention might be needed in terms of altering HDL code.
FPGAs have dedicated primitives like block RAMs, DSPs which contribute to a good percentage of the total power. These primitives have clock enables which can be leveraged similar to fl ip-fl ops if there are clock gating structures on these.
Fig.9.3 Using BUFGCE for clock gating
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