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System Generator provides facilities and services that enable expression and verifi - cation of DSP data paths rapidly. However, a system implemented on FPGA includes more than the DSP data path such as interfacing with memory, bringing data in from sensors through ADCs and IOs or HDMI interface. Other Xilinx tools such as Vivado IP Integrator (Chap. 7 ) or RTL fl ow with Pin Planner are more suitable for this purpose. To aid with these user fl ows, System Generator provides IP Catalog as a compilation target as shown in Fig. 8.9 .
In this compilation mode, in addition to generating products from System Generator that are synthesizable using Vivado, the output products are also pack- aged into an IP located in the IP folder under target directory. This IP can be used in an IPI project or instantiated in an RTL project. More on IPI is covered in Chap. 7 , and on using an IP in an RTL project is covered in Chap. 3 .
Fig. 8.9 IP Catalog as a compilation target
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