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RTL Test Bench
Along with the RTL and IP that represents the System Generator design in Simulink, you can also optionally generate a self-verifying RTL test bench . On invoking code generation, the design is simulated in Simulink where Gateway In and Gateway Out blocks log the data they consume and produce into fi les with .dat extensions. Running the RTL simulation of the test bench uses the data fi les generated from Gateway In s as stimuli and compares the results of RTL simulation on the output ports of the module with the data fi les generated from Gateway Out . The RTL test bench can be reused to verify the results of synthesis of the System Generator module as well as implementation.
System Generator modules are generally a submodule of a larger design, typi- cally a DSP data path. The RTL test bench allows users to verify the System Generator module in isolation. Also the RTL test bench along with a System
Fig. 8.8 General fl ow to close on a System Generator module
Generator module provides a handoff mechanism to an RTL developer responsible for integrating the system. This will help the RTL developer to become familiar with the System Generator submodule of a larger design.
Many DSP algorithms require processing of a very large number of samples for rati- fi cation. For example, a receiver in a communications pipeline may need to process millions of samples to generate BER numbers. Often times even cycle accurate simulation in Simulink may take many days of simulation to verify that the algo- rithm is correct. To help with reducing the simulation run times, System Generator also has an important feature called Hardware Co - simulation that accelerates Simulation by using one of Xilinx’s Hardware Evaluation Boards.
To use Hardware Co-simulation the design must be compiled for a specifi c target board. This is done by setting the compilation target for Hardware Co-simulation.
Invoking code generation compiles the design into a bitstream that includes the user design as expressed in Simulink and a communication interface to pass data from the host PC to the FPGA board. Two types of communication interfaces are supported including JTAG and Ethernet. In general Hardware Co-simulation helps only if the Simulink simulation time is on the order of 6 h or more. This is because for each iteration, the design must fi rst be implemented.
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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