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System designers and prototyping teams have been using FPGAs to their benefifi t. FPGA tools are available to provide RTL to FPGA mapping. If you have a prototyping environment, the additional activities for going to emulation include:
1. Creation of a synthesizable and reconfi gurable testbench.
2. Addition of instrumentation into design for advance debug purposes.
3. Mapping of complex design blocks like IOs, SERDES, DSP blocks, and block
RAMs to the FPGA.
4. Remapping of complex clocking structure of the device to the FPGA-based
PLLs and clock controllers.
5. Mapping of design IOs to the FPGA IOs to obtain connectivity to the external
targets (JTAG, UART, etc.).
6. For designs which require multiple FPGAs:
(a) Logic Partitioning : Partitioning of the design into chunks of logic to fifi t into individual FPGAs. This depends on the size of the design and the size of placeable gates on the FPGA. The logic and memory closely associated with the said logic are grouped together into pieces which fifi t on the same FPGA.
(b) Pin Partitioning : Partitioning of the design with appropriate pin count across FPGAs. This depends on the hardware board design and is usually fifi xed for a particular board.
The additional activities for going to emulation from a simulation setup include:
1. Observability: Simulation allows to see the waveforms for all signals at all times. The waveforms are directly dumped into a hard disk during runtime. In an FPGA, there are limited logic and memory resources. So complete runtime waveform dumping is not possible. Thus, you have to add instrumentation to trigger the start of waveform dumping for a known limited number of signals and for a known limited amount of time. Furthermore, you need to build in a mechanism to retrieve the waveform data from the FPGA block RAMs. Xilinx Vivado provides ILA core for doing this—as explained in Chap. 17 .
2. Controllability : For some tests, a specififi c pin (say: reset ) may need to be kept at a desired value for a specififi c duration. In simulation you can force the signal then release it. A similar ability needs to be provided when doing emulation using FPGAs. Xilinx Vivado provides VIO.
3. Memory initialization : The DUV usually contains BOOTROM which needs to be programmed (preloaded) with the appropriate bitmapped code. The testbench could have other memory models of flfl ash, DDR, etc. In the simulation environment, the memory load ( $readmemb ) and dump can be used. A similar ability is required for emulation using FPGAs.
Xilinx FPGAs and the Vivado tool set provide the methods and means to make all of the above possible.
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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