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The Isolation Design flfl ow was developed to allow independent functions to operate on a single chip with the suffifi cient level of isolation required for various certififi cations. Applications of this flfl ow include redundant type I cryptographic modules or resident safety-critical functions.
There are a few unique design details that you must adhere to, in order to achieve an FPGA-based isolation design flfl ow solution. The requirements that a design needs to meet in order to take advantage of the isolation design flfl ow are shown in Fig. 19.6 and include:
• Isolated Module : Each function to be isolated must be in its own level of hierarchy and reside within its own physical region of the FPGA.
• Fence : This is a set of unused tiles with no logic or routing used—to separate the
isolated modules . This has to be a minimum of one non-routing tile in depth.
• Trusted Routing : On-chip communication between isolated functions is achieved
through the use of trusted routing . Vivado chooses one to one routes along the
coincident physical borders of isolated modules .
• Top Level : Only global logic including BUFG and MMCM is allowed at the top
level. All other logic must reside inside an isolated module .
• IOBs : IOBs can be instantiated or inserted inside the isolated modules .
The isolation design flfl ow relies on you logically partitioning the design such that each isolated module resides in a different hierarchical block directly under the top level of the design. Once this is achieved, there are a few steps that you need to follow:
1. Set the HD.ISOLATED property on each isolated module .
2. Set the HD.ISOLATED_EXEMPT property on any logic at the top level.
3. Synthesize the design.
4. Floorplan the isolated modules .
5. Run isolation verifi cation on the fl oorplan to ensure adequate fencing.
6. Implement the design.
7. Run isolation verifi cation on routed design to ensure correct isolation.
8. Generate bitstream.
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