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Hierarchical design ( HD ) flfl ows enable you to partition a design into smaller modules that can be implemented independently, before choosing whether or not to reuse the results at the top level of the design.
Hierarchical design flfl ow provides the ability to take a given module, synthesize and implement it independently, and then reuse the results in an overall design. There are two parts of the hierarchical design flfl ow: Module Analysis and Module Reuse .
In Module Analysis you can synthesize, implement, and conduct resource or timing analysis on a module without the need of special wrappers. The implementation is done with no IOs or clocks . These need to be explicitly specififi ed if needed. The implementation results can then be saved for reuse.
In Module Reuse you take the results of an implemented Module Analysis run, lock-down, and reuse them in a top-level design. There are two variants of Module Reuse : bottom up and top down .
Bottom-up reuse is where you ran the Module Analysis flfl ow without prior knowledge of the top-level design. This allows you to reuse the same Module Analysis results for multiple top-level designs on the same device.
Top-down reuse is where you use a top-level design and flfl oorplan to generate out-of-context constraints, to be used by independent Module Analysis runs, before reusing the results to assemble the top-level design. This flfl ow allows a team to work simultaneously on portions of the same design.
The Vivado tool flfl ow for hierarchical design is split into Module Analysis and Module Reuse . To run the Module Analysis , use the following steps:
1. Synthesize the module or IP in out-of-context or bottom-up synthesis.
2. Set the HD.PARTITION property on the module.
3. Add clock and timing constraints specifi c to that module.
4. Floorplan the area into which the module will be placed.
5. Add out-of-context constraints including HD.CLK_SRC property as well as partition pin locks and optimization constraints.
6. Implement the module and save the placed and routed module results.
To run the Module Reuse fl ow, use the following steps:
1. Synthesize the top level with black boxes for module instances.
2. Set HD.PARTITION property on the module instances.
3. Read in results from Module Analysis run, into the relevant instances.
4. Lock the implementation results of the modules that have just been read in. This
can be done at either logical, placement, or routing level.
5. Implement the remainder of the design.
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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