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The PCI Express specififi cation requires the PCIe link to be ready to link train with a peer within 120 ms after power is stable. This is nominally referred to as the 100 ms boot time . Meeting this requirement is a challenge for large FPGAs due to the size of the bitstream and typical confifi guration rates available. Tandem support in 7-Series and UltraScale allows the PCIe to be up and ready to link train within the required timeframe.
The Tandem flfl ow allows the PCIe block in the FPGA to meet the 120 ms boot-up requirement by splitting the confifi guration into two stages:
• Stage 1 : The minimum PCIe functionality needed to ensure device discovery is confifi gured. This stage requires a very small bitstream that can be confifi gured in much less than 120 ms and is capable of handling all transactions during enumeration time.
• Stage 2 : The rest of the FPGA is confifi gured with the user design after the PCIe block becomes active.
There are two tandem confifi guration methods supported, Tandem PCIe and Tandem PROM . Both methods employ the two-stage bitstream confifi guration principle outlined above. In both cases, Stage 1 is confifi gured via an on-board PROM which resides on the board, in order to meet the 120 ms start-up time. The main difference is in the delivery of the Stage 2 bitstream; Tandem PROM uses the same on-board PROM, while in Tandem PCIe , the PCIe interface is used. Unlike Partial Reconfifi guration , the Tandem approach never reconfifi gures a frame. Every frame in the device is confifi gured only once. If dynamic updates to the user application are required, Partial Reconfifi guration or the Field Update flfl ow should be used.
The tandem with Field Update flfl ow was introduced starting with the UltraScale architecture; Tandem confifi guration methods are used to initially confifi gure the device when the power is turned on, followed by Partial Reconfifi guration of the full Stage 2 logic. Thus, the Field Update flfl ow allows multiple Stage 2 bitstreams to be downloaded on demand, without the need to reconfifi gure the Stage 1 , thus maintaining the PCIe linkup throughout. Figure 19.5 shows how the Tandem PROM , Tandem PCIe, and Tandem with Field Update flfl ows operate.
The support for the tandem and tandem with Field Update flfl ows is embedded within the PCIe core. The PCIe core and example design should be used as the foundation of any applications that utilize these flfl ows. The following steps outline the tool flfl ow to be followed by you:
1. Select the type of tandem fl ow required and generate the core.
2. Open the example project, and implement the example design.
3. Use the IP and XDC from the example project as the basis of your project.
4. Synthesize and implement your design.
5. If using tandem with Field Update , follow steps 6–10 from Sect. 19.1.4 .
6. Generate bitstream and PROM fi les required.
Tandem PROM and Tandem PCIe flfl ows both rely on initial PROM confifi guration of Stage 1 followed by Stage 2 being confifi gured via the external confifi guration pins in Tandem PROM or via the PCIe link in Tandem PCIe.
In Tandem PCIe, the PCIe IP provides an internal interface to the confifi guration memory. In 7-Series this is achieved by an explicit connection to the ICAP (internal confifi guration access port). This connection is disabled after Stage 2 confifi guration. In UltraScale the connection to the confifi guration memory is made via the MCAP
(media confifi guration access port ) which is embedded inside the PCIe block. This connection remains enabled even after Stage 2 confifi guration is complete. Access to the MCAP after Stage 2 is the key enabler for the Tandem Field Update flfl ow.
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