IPI Flow

Design Entry Within BD Canvas

The basic method of design entry in a project mode within IPI relies on instantiating the IPs from the IP Catalog in the block design canvas. Section 3.2 explains about IP Catalog . While creating a design, you need to just drag and drop the IP from the

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Fig. 7.3 Selection window for packaging

catalog in the canvas or can directly add to the canvas by clicking the “+” button. The IPs instantiated in the design can be individually confi gured based on the design requirement provided that the IP under work has those options available while it was being packaged:

• Stitching the design

Various blocks of IP modules instantiated within the block design canvas can be respectively connected to structure the system. Block design by default automati- cally identifi es the AXI interconnect interfaces, clock, and reset connections. This assists the users in stitching the design together.

• Ports

Create Port option within IPI provides you with more control in specifying the input and output, the bit-width, and the type (such as clk, reset, and data). With this option you can also specify the frequency for clock ports. There is also a provision for making the port from the IP external meaning that it would be promoted to the top level.

Designer Assistance

Another powerful feature offered by IP integrator is the Designer Assistance which includes block automation and connection automation. To narrate it in brief, this feature provides users with suggestions to establish potential connections between interfaces of the compliant IPs:

• Connection automation This feature assists the users in connecting the AXI interfaces, reset/clock ports, and/or ports of the IPs to external I/O ports. These ports if made external will appear in the top-level HDL wrapper, and an appropriate XDC constraint would be required to be defi ned for them.

• Block automation

This feature is available only when an embedded processor such as the Zynq 7000 Processing System or Zynq MPSoC or MicroBlaze processor or some other hierarchical IP such as an Ethernet is instantiated in the IP Integrator block design. This feature allows users to confi gure the related IPs based on their design require- ments. It comes with a certain set of options, which you can choose from to confi g- ure the IP, thus bypassing the need to manually confi gure the IP.

For example, in Fig. 7.4 , once the MicroBlaze processor IP is instantiated in the design, the block automation becomes available.

On clicking the Run Block Automation , a pop-up shows up as shown in Fig. 7.5 , which allows you to confi gure the MicroBlaze IP.

Once confi gured, the block design updates to refl ect the changes selected, and a new set of IPs also appear in block design based on the set of selection.

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Fig. 7.4 Block automation notifi cation

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Fig. 7.5 Block automation confi guration settings for MicroBlaze

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Fig. 7.6 Block design after execution of block automation

As seen in Fig. 7.6 , the Connection Automation gets activated as it has identi- fi ed the potential AXI and/or clock/reset ports for which it can assist you to establish connection. On clicking the Run Connection Automation , a window as shown in Fig. 7.7 pops up. You can then choose from the available set of selections for these ports.

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Fig. 7.7 Confi guration settings for connection automation

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Fig. 7.8 Address editor

Address Editor

The Address Editor tab provides the slave address mapping corresponding to the master interface. However, please note that the Address Editor tab only appears if the block design contains an IP block that functions as an AXI master interface (such as the MicroBlaze processor) or if an external bus master (outside of IP Integrator ) is present.

As can be seen in Fig. 7.8 , the data and the instruction cache of the MicroBlaze are respectively mapped to the block RAM and local memory, the address of whom is depicted on the offset address.

• Address Map

Master interfaces reference an assigned memory range container called address spaces . Slave interfaces reference a requested memory range container called a memory map. The address space names are related to the usage by the master inter- face to which it corresponds to. It represents which slaves are mapped to which address space of the master. The entire address map is available in a separate tab called an Address Editor tab within the IPI layout.

Parameter Propagation

While designing with IPs in block design, it is important that the confi guration user parameters are propagated to the IP blocks connected. It enables an IP to auto- update its parameterization based on how it is connected in the design. For example, the clock frequency set in one of the IP blocks gets propagated through the design. IP can be packaged with specifi c propagation rules, and IP Integrator will run these rules as the block design is generated. However, if the IP cannot be updated to match properties based on its connection, an error is reported to highlight the poten- tial issues in the design.

Validate Design

Validate design enables you to run a comprehensive design rule check as your design is being consolidated which ensures that the parameter propagation, address assignment as described above, and other aspects of the design creation are correct.

In short it ensures the completeness of the design. You can click on the icon available in either the toolbar pane or in the BD canvas pane to run validation checks.

Generate Design

In order to generate the necessary source fi les from the various IPs used in the block design which are to be used by synthesis and implementation runs, IPI provides a feature to generate the block design called Generate Block Design available in the fl ow navigator upon successful completion of validation of design. It generates vari- ous source fi les like the HDLs respective to the IPs, constraints, and register level fi les (for processor if any in BD) associated with the individual IP components. If this option is run before validate design , this process will fi rst invoke validate design ; ensure that there are no DRC in the design and will then generate the respec- tive output products. These outputs can be seen in the Vivado Sources pane. Based on the language setting of the project, the output products will be generated accord- ingly (provided the IP is packaged accordingly).

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Fig. 7.9 Creating an HDL wrapper

Top-Level RTL Wrapper

The block design can be either the topmost level of the design or it can be instanti- ated in an RTL which then can be the top level of the design. If the block design is the topmost in the hierarchy of the IPs, IPI provides a way to generate the RTL wrapper for the same which is used in the synthesis fl ow as shown in Fig. 7.9 . Based on whether the project settings have been set to either Verilog or VHDL, the top-level RTL wrapper will be generated in a respective HDL.

Export Hardware Defi nition

This feature allows you to transfer the hardware design information to the Software Development Kit ( SDK ). It is mainly useful in a hardware-software ecosystem. Usually in a processor-based system, when there is a programmable logic (PL) also present in the design, the hardware defi nition is exported after bitstream generation which thus includes the complete hardware and software confi guration. However, in some cases when there is no PL present, there is no need to generate bitstream, and the hardware information can be exported right after generation of output products.

Creating an Example Design

Vivado provides a way to ensure that you get started with some reference design created in IPI. It has a predefi ned set of example projects being embedded which can be created at the beginning to the project.

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Fig. 7.10 Creating an example design

Figure 7.10 shows availability of reference designs which are available for you. Based on the selection made, the tool generates an IPI-based design which acts as a template design for you. You can alter this design, based on your requirements.

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