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Home > FPGA Technical Tutorials > Designing with Xilinx FPGAs Using Vivado > Vivado IP Integrator > Terminology

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Xilinx FPGA FPGA Forum

Terminology

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Block Design (BD)

Vivado IDE provides the capability to create a workspace for you wherein you can graphically create design systems in an IPI-provided canvas, stitch the design together using the automation tools, ensure the correctness of the design, and generate the design. The block design can be created in both project and non-project mode (explained in Chap. 2 ). As stated above, one of the major features of the block designs is the graphical canvas which allows you to instantiate IP blocks from the IP Catalog and construct designs. Figure 7.1 shows the block design creation and the canvas of the BD. 

Automation Notifi cations

One of the key aspects of IPI is the provision of the connection and board automa- tion. Whenever IPI identifi es potential interface connections between various IP blocks, it notifi es you about the possible availability through a hyperlink visible at the top of the canvas, as shown in Fig. 7.2 . For example, clock, reset, and AXI con- nections between the AXI-compliant IPs are covered in this automation. Detailed explanation is covered under Sect. 7.3.2 (Designer Assistance). 

Hierarchical IP

IPI provides a feature where an IP can pack another block design within itself, thus offering another level of block design inside top level to display the logical confi guration of the parent. These hierarchical blocks enable you to view the contents of the

BD canvas of IPI.png

Fig. 7.1 BD canvas of IPI

IPI notifying about automation availability.png

Fig. 7.2 IPI notifying about automation availability

block but do not allow to edit the hierarchy. Changes are permitted only to the top level exposed parameters available in the confi guration window of the IP.

Packaging

IPI also provides a feature wherein you can package the entire block design after it has been validated and functionality has been proven. This allows you to reuse the IP block design in other projects as well. Figure 7.3 depicts the selection window for packaging the project. 

Once the block design is packaged, the tool copies the necessary fi les in the speci- fi ed directory and adds the IP repository to the project locally. The properties associ- ated with the package can be changed while packaging the design, thus enabling you to use the block design in other projects. 

  • XCV200-5PQ240C

    Manufacturer:Xilinx

  • FPGA Virtex Family 236.666K Gates 5292 Cells 294MHz 0.22um Technology 2.5V 240-Pin PQFP
  • Product Categories: Résistances SMD à puce

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XCV200-6BG352I

    Manufacturer:Xilinx

  • FPGA Virtex Family 236.666K Gates 5292 Cells 333MHz 0.22um Technology 2.5V 352-Pin Metal BGA
  • Product Categories:

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC4028XL-2HQ160C

    Manufacturer:Xilinx

  • FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 160-Pin HSPQFP EP
  • Product Categories: FPGAs

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC4028XL-3BG352C

    Manufacturer:Xilinx

  • FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 352-Pin Metal BGA
  • Product Categories: FPGAs

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC5VFX130T-2FFG1738C

    Manufacturer:Xilinx

  • FPGA Virtex-5 FXT Family 65nm Technology 1V 1738-Pin FCBGA
  • Product Categories: FPGAs (Field Programmable Gate Array)

    Lifecycle:Active Active

    RoHS:

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