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We can put these elements together in simple models that implement basic filter blocks in any configuration we require, as always taking care to ensure that overflow errors are checked for in practice.
To demonstrate this, we can implement a simple low pass filter using the basic block diagram shown in Figure 9.2.
We can create a simple test circuit that uses the individual models we have already shown for the sum and delay blocks and apply a step change and observe the response of the filter to this stimulus. Clearly, in this case, with unity gain the filter exhibits positive feedback and so to ensure the correct behavior we use the divide by 2 model zdiv2 in both the inputs to the sum block to ensure gain of 0.5 on both. These are not shown in the figure. The resulting VHDL model is shown in the following code (note the use of the zdiv2 model):
1 library ieee;
2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all;
4
5 entity tb is
6 end entity tb;
78 architecture testbench of tb is
9
10 signal clk : std_logic := ’0’;
11 signal x : signed (7 downto 0):=X”00”;
12 signal y : signed (7 downto 0):=X”00”;
13 signal y1 : signed (7 downto 0):=X”00”;
14 signal yd : signed (7 downto 0):=X”00”;
15 signal yd2 : signed (7 downto 0):=X”00”;
16 signal x2 : signed (7 downto 0):=X”00”;
17
18 component zsum
19 generic (
20 n : integer := 8
21 );
22 port (
23 signal zin1 : in signed(n−1 downto 0);
24 signal zin2 : in signed(n−1 downto 0);
25 signal zout : out signed(n−1 downto 0)
26 );
27 end component;
28 for all : zsum use entity work.zsum;
29
30 component zdiff
31 generic (
32 n : integer := 8
33 );
34 port (
35 signal zin1 : in signed(n−1 downto 0);
36 signal zin2 : in signed(n−1 downto 0);
37 signal zout : out signed(n−1 downto 0)
38 );
39 end component;
40 for all : zdiff use entity work.zdiff;
41
42 component zdiv2
43 generic (
44 n : integer := 8
45 );
46 port (
47 signal zin : in signed(n−1 downto 0);
48 signal zout : out signed(n−1 downto 0)
49 );
50 end component;
51 for all : zdiv2 use entity work.zdiv2;
52
53 component zdelay
54 generic (
55 n : integer := 8
56 );
57 port (
58 signal clk : in std_logic;
59 signal zin : in signed(n−1 downto 0);
60 signal zout : out signed(n−1 downto 0)
61 );
62 end component;
63 for all : zdelay use entity work.zdelay;
64
65 begin
66 clk <= not clk after 1 us;
67
68 GAIN1 : zdiv2 generic map (8) port map ( x, x2);
69 GAIN2 : zdiv2 generic map (8) port map ( yd, yd2);
70 SUM1 : zsum generic map (8) port map ( x2, yd2, y );
71 D1 : zdelay generic map (8) port map ( clk, y, yd );
72
73 x <= X”00”, X”0F” after 10 us;
74 end architecture testbench;
The test circuit applies a step change of X00 to X0F after 10 µs, and this results in the filter response. We can show this graphically in Figure 9.3 with the output in both hexadecimal and analog form for illustration.
It is interesting to note the effect of using the zdiv2 function on the results. With the input of 0F (binary 00001111) we lose the LSB when we divide by 2, giving the resulting input to the sum block of 00000111 (7) which added together with the division of the output gives a total of 14 as the maximum possible output from the filter. In fact, the filter gives an output of X0D or binary 00001101, which is two down from the theoretical maximum of X0F and this highlights the practical difficulties when using a coarse approximation technique for numerical work rather than a fixed or floating point method. On the other hand, it is clearly a simple and effective method of implementing a basic filter in VHDL.
Later in this book, the use of fixed and floating point numbers are discussed, as is the use of multiplication for more exact calculations and for practical filter design; where higher accuracy is required, then it is likely that both these methods would be used. There may be situations, however, where it is simply not possible to use these advanced techniques, particularly a problem when space is at a premium on the FPGA and, in these cases, the simple approach described in this chapter will be required.
There are numerous texts on more advanced topics in digital filter design, and these are beyond the scope of this book, but it is useful to introduce some key concepts at this stage of the two main types of digital filter in common usage today. These are the recursive (or Infinite Impulse Response, IIR) filters and nonrecursive (or Finite Impulse Response, FIR) filters.
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