Basic Hardware Resources

According to Figure 2.1, the basic hardware resources of FPGAs are LBs, IOBs, and interconnection resources.

Logic Blocks

LBs are intended to implement custom combinational and sequential func- tions. As a consequence, they mainly consist of reconfigurable combinational functions and memory elements (flip-flops/latches). The combinational part can be implemented in different ways (e.g., with logic gates or MUXs), but nowadays, lookup tables (LUTs, introduced in Chapter 1) are the most fre- quently used combinational elements of LBs. The differences among LBs from different vendors (or different FPGA families from the same vendor) basically refer to the number of inputs of the LUTs (which define the maxi- mum number of logic variables the combinational function implemented in the LUT can depend on), the number of memory elements, and the con- figuration capabilities of the LB. Two sample LBs are shown in Figure 2.5, from Microsemi’s IGLOO2 (Microsemi 2015a) and Achronix’s Speedster22i HD1000 devices (Achronix 2015), respectively. 

The complexity of LBs depends on the kind of applications a given FPGA family targets. The LB in Figure 2.5a corresponds to one of the simplest 

FIGURE 2.5 (a) LE from Microsemi’s IGLOO2 and (b) heavy logic cluster from Achronix’s Speedster22i HD1000 devices.

existing structures. It allows logic functions with up to four inputs to be implemented and includes just one flip-flop, which can be used either independently or to memorize the output of the LUT. In addition, specific lines (CIN and CO) allow carry signals to be propagated from the LB to a contiguous one. Carry propagation chains are a typical resource in any LB, which simplifies the efficient implementation of widely used func- tions such as counters or adders. 

On the other hand, the LB in Figure 2.5b is more complex. It consists of two four-input LUTs, one embedded adder, and two flip-flops. Using the corresponding MUX, each LUT can implement a single five-input function. In addition, LUTs and MUXs can be combined to implement certain six- to nine-input functions (Achronix 2015). Embedded adders, supporting 2 bit operands, allow addition-based computations to be accelerated. Finally, the availability of two flip-flops per LB targets register-intensive solutions, such as pipelining. The remaining elements, mainly MUXs, provide configu- rability, enabling many different combinations of the other resources to be configured as well as easing routability of input and output signals. 

In the vast majority of FPGAs, basic LBs are grouped in blocks of higher hierarchy sharing specific interconnection resources, allowing more complex functions to be implemented with short additional delays. Also, flip-flops can be combined to create shift registers, delay lines, or distributed* memo- ries (ROM, single- or dual-port RAM, or FIFOs). 

A specific solution (Achronix picoPIPE) aimed at the implementation of pipelined datapaths without the need for adding intermediate flip-flops/ registers (therefore avoiding modifications to be required in the original, nonpipelined logic structure) is shown in Figure 2.6 (Achronix 2015). It is 

FIGURE 2.6 (a) Achronix picoPIPE building blocks and (b) pipeline stages.

* So called because they are built using distributed logic.

based on a handshake-controlled, asynchronous propagation of data, instead of the usual clock-synchronized propagation of conventional FPGA logic. 

There are four basic building blocks in Figure 2.6:

• Functional elements, which not only implement the target combinational logic but also handshake data input and output, thus ensuring

only valid data are propagated.

• Connection elements, which provide resources for both connectivity and storage (flip-flops). Therefore, they can act as simple data repeaters or as registers, enabling either asynchronous or synchronous computations to be implemented.

• Links to communicate functional elements.

• Boundary elements, used as interface between picoPIPE and conventional FPGA logic. Data entering (exiting) the picoPIPE fabric must pass through ingress (egress) boundary elements.

The use of pipeline stages like the ones shown in Figure 2.6 allows any logic function to be implemented using the same logic structure it would have in a nonpipelined conventional FPGA implementation and implicitly add pipeline stages as required to shorten propagation delay times, reaching operating frequencies up to 1.5 GHz (Achronix 2008). A sample comparison between conventional and picoPIPE implementa- tions is depicted in Figure 2.7 (interconnection resources are described in Section 2.3.3). 

FIGURE 2.7 Comparison between conventional and picoPIPE implementations.

I/O Blocks

IOBs serve as links between device pins and internal resources. Their main elements are programmable bidirectional buffers and flip-flops to synchro- nize I/O and configuration signals, as shown in Figure 2.8 (Altera 2012; Xilinx 2014a; Microsemi 2015b). 

Similar to the case of LBs, IOBs with different levels of complexity are available in the different families of current FPGA devices. However, they all share some common features: 

• Input data can either be directly connected to the internal resources or pass through a memory element. Similarly, output data can pass through a memory element or bypass it. 

• Memory elements can be configured as flip-flops or latches. 

• Bidirectional buffers support different voltage levels (1.2, 1.5, 1.8, 2.5, 3.0, and 3.3 V) and different I/O standards (single-ended, differential, or voltage-referenced). The most commonly available ones are low-voltage TTL, low-voltage CMOS, stub series-terminated logic (SSTL), differential SSTL, high-speed transceiver logic (HSTL), differential HSTL, high-speed unterminated logic (HSUL), and low- voltage differential signaling (LVDS). 

FIGURE 2.8 Bidirectional IOB.

FIGURE 2.9 I/O banks.

IOBs are grouped in banks sharing common resources and, usu- ally, configuration details (Altera 2015b; Microsemi 2015b; Xilinx 2015a), as shown in the example in Figure 2.9. Each bank can be con- figured to support a different I/O standard (in some advanced device families, several standards can be combined in the same bank). Since each standard has its own specifications for voltages, currents, types of buffer, and types of termination, the ability to adapt the same FPGA to simultaneously use several I/O standards allows it to be connected to circuits operating under different electrical conditions (e.g., different power supply voltages) without the need for external conditioning circuitry. This simplifies PCB design and decreases design time, in turn significantly reducing cost. 

• Programmable control of the output current for some I/O standards. This feature allows the output buffer of the IOB to comply with the I OH and I OL specifications of the configured standard, reducing simultaneous switching output effects and, in turn, noise. 

• Programmable control of the output slew rate (rising and falling), which can be independently configured for each pin at different lev- els (available levels vary among devices), for example, slow or fast. For outputs operating at high frequencies, fast configurations should be used, but attention must be paid to possible signal reflection prob- lems and noise transients during switching. 

• Programmable pull-up and pull-down resistors. 

• Programmable delay lines to control setup and hold times in input flip-flops/latches and clock-to-output propagation times in out- put flip-flops/latches or to delay input clock signals. 

• Support for double data rate (DDR) I/O. This implies IOBs include at least two input and two output flip-flops and two clock signals with a 180° phase shift between them. Flip-flops can be configured to capture data in the same edge of both clocks or in opposite edges, thus allowing different data alignment modes to be implemented. 

• Programmable output differential voltage (V OD ). This allows the right trade-off between voltage margin of the external circuit (which increases for higher V OD ) and FPGA power consumption (which decreases for lower V OD ) to be achieved for each particular application. 

As may be noticed in Figure 2.9, IOBs can include specialized elements in addition to the ones mentioned earlier. These functionalities may only be available in the most complex (and expensive) devices. Two of the most useful ones, SerDes blocks and FIFO memories, are described in Sections 2.3.2.1 and 2.3.2.2.

SerDes Blocks

SerDes blocks are serial–parallel (input deserializer) and parallel–serial (out- put serializer) conversion circuits to interface digital systems with serial communication links. They significantly ease the implementation of systems with high data transfer rate requirements, such as in video applications, high- speed communications, high-speed data acquisition, and serial memory access. 

In some FPGAs, SerDes blocks can only work with differential signals; that is, they can only be used when the corresponding IOBs are configured to work in a differential I/O standard. In other devices, they can work with both single-ended and differential signals. 

SerDes can support different operating modes and work at different data transfer rates (e.g., single data rate or DDR modes). In some cases, they can be connected in chain to achieve higher rates. 

A SerDes block from Altera’s Arria 10 family (Altera 2015b) is shown in Figure 2.10. The upper part corresponds to the output serializer, whereas the input deserializer is depicted in the lower part. One of the most critical issues in the design of this kind of circuits is related to the requirements imposed on clock signals. Due to this, some FPGAs include dedicated clock circuits (independent from global clock signals) in their SerDes blocks (e.g., I/O phase-locked loop [PLL] in Figure 2.10). 

The input deserializer usually includes a bit slip module to reorder the sequence of input data bits. This feature can be used, for instance, to correct 

FIGURE 2.10 Altera’s Arria 10 family SerDes block.

skew effects among different input channels (like in Altera’s Arria 10 devices) or to detect the training patterns used in many communication standards (like in Xilinx’ Series 7 devices). 

In some FPGA families (e.g., Altera’s Arria 10), the input deserializer also includes a dynamic phase alignment circuit (DPA in Figure 2.10) that allows input bits to be captured with minimum skew with regard to the deserial- izer’s clock signal. This is accomplished by choosing as clock signal, among several of them with different phases, the one with minimum phase shift with regard to input bits. 

FIFO Memories

I/O FIFO memories are available in some of the most advanced FPGAs (like Xilinx’ Series 7 devices). They are mainly intended to ease access to exter- nal circuits (such as memories) in combination with SerDes or DDR I/O resources, but can also be used as fabric (general-purpose) FIFO resources. 

Interconnection Resources

Interconnection resources form a mesh of lines located all over the device, aimed at connecting the inputs and outputs of all functional elements of the FPGA (LBs, IOBs, and specialized hardware blocks—described in Section 2.4). They are distributed in between the rows and columns of func- tional elements, as shown in Figure 2.11. 

Interconnect lines are divided into segments, trying to achieve the mini- mum interconnect propagation delay times according to the location of the elements to be connected. There are segments with different lengths, depending on whether they are intended to connect elements located close to each other (short segments) or in different (distant) areas of the device (long segments). 

FIGURE 2.11 General and local FPGA interconnection resources.

For specific signals expected to have high fan-out, for example, clock, set, or reset (global) signals, special lines are used, covering the entire device or large regions in it. For instance, clock signals have a dedicated inter- connection infrastructure, consisting of global lines and groups of regional lines, each group associated with a specific area of the device, as discussed in Section 2.4.1. The stacked silicon interconnect technology used in some Xilinx’ Virtex-7 devices allows performance to be improved, thanks to ultra- fast clock lines and a fast type of interconnection resource called superlong lines (Saban 2012). 

In order for a particular interconnection to be built, several segments are connected in series by means of crossbar matrices.* Since LBs are the most 

* Like in the case of LBs and IOBs, the terminology for interconnection resources varies depending on the FPGA vendor.

abundant resources and have a significant number of input and output signals (as can be noticed in Figure 2.5), they are usually first connected to a dedicated crossbar matrix shared by several of them (local interconnec- tion resources) and, from it, to the general FPGA interconnection resources (Xilinx 2014b; Achronix 2015; Altera 2015a; Microsemi 2015c), as shown in Figure 2.11. 

Interconnection delays are a critical factor in the performance of FPGA designs. They depend on the type of resources used, the number of matri- ces to be crossed, and the distance to be traveled by signals. Because of this, the assignment (placement) of the functional blocks of a given circuit to the best possible actual hardware resources in the FPGA is a key factor in achieving the best possible performance. Software design tools should provide suitable placements, but in some cases (in particular for complex designs requiring the use of most of the available hardware resources), the best performance can only be obtained with some designer intervention at the device floorplan level (or, if feasible, by using higher-end, more expen- sive, devices).