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Despite, or perhaps because of, 25 years of progress, the first law of prototyping is still pertinent. It is true that many FPGA-based prototyping projects require only one FPGA and this is usually true for IP block verification and in-lab feasibility projects. However, SoC projects are by their nature large and getting larger and while FPGA devices are at the leading edge of silicon development and also getting larger year-on-year, we will probably still need multiple of the largest FPGA devices to prototype a full SoC.
This means partitioning of the SoC design into multiple FPGAs for which we recommend using specialist EDA tools. These will allow us to partition interactively or automatically, the former giving the better results but taking longer.
The typical size of a prototype is between one and ten devices but with sophisticated automated partitioning and programmable interconnectivity, prototypes up to 20 devices are possible. As each device is already just over four million ASIC gates, this represents a design up to 80 or 90 million SoC gates which is way above the size of the majority of SoC designs today.
When the SoC design is partitioned over multiple FPGAs, we will need to perform some extra design work in order to maintain the design connectivity, the clock networks, and the reset and start–up synchronization. These are all explained in chapter 8.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
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