Main FPGA Architectures

The basic architecture of most FPGAs is the one shown in Figure 2.1, based on a matrix of configurable hardware basic building blocks (LBs,* introduced in Chapter 1) surrounded by IOBs that give FPGA access to/from external devices. The set of all LBs in a given device is usually referred to as “dis- tributed logic” or “logic fabric.” An LB can be connected to other LBs or to IOBs by means of configurable interconnection lines and switching matrices (IL, as also introduced in Chapter 1) (Kuon et al. 2007; Rodriguez-Andina et al. 2007, 2015). In addition to distributed logic, aimed at supporting the development of custom functions, FPGAs include specialized hardware blocks aimed at the efficient implementation of functions required in many practical appli- cations. Examples of these specific resources are memory blocks, clock management blocks, arithmetic circuits, serializers/deserializers (SerDes), transceivers, and even microcontrollers. In some current devices, analog functionality (e.g., ADCs) is also available. The combination of distributed logic and specialized hardware results in structures like the ones shown in Figure 2.2 (Xilinx 2010; Microsemi 2014; Achronix 2015; Altera 2015a). 

* LBs receive different names from different FPGA vendors or different families from the same vendor (e.g., Xilinx, configurable logic block [CLB]; Altera, adaptive logic module [ALM]; Microsemi, logic element [LE]; Achronix, logic cluster [LC]), but the basic concepts are the same. This also happens in the case of IOBs.

FIGURE 2.2

(a) Altera MAX 10, (b) Microsemi’s Fusion, (c) Xilinx’s Spartan-6, and (d) Achronix’s Speedster22i HD architectures. Note: In December 2015, Intel Corporation acquired Altera Corporation. Altera now operates as a new Intel business unit called Programmable Solutions Group.

The main drawback of the matrix architecture, related to the number of IOBs required in a given device, affects complex FPGAs. As more distributed and specialized logic is included in a given device, more IOBs are also required, increasing cost. Another limitation of this architecture comes from the fact that power supply and ground pins are located in the periphery of the devices, and then voltage drops inevitably happen as supply/ground currents flow to/from the core from/to these pins. A third limitation is that the ability to scale specialized hardware blocks depends on the amount of distributed logic available in their vicinity. 

To mitigate these limitations, vendors have developed column-based FPGA architectures (Xilinx 2006; Altera 2015b) like the one depicted in Figure 2.3. 

FIGURE 2.3 Column-based architecture.

First, in these architectures, there is no dependency of the number of IOBs on the amount of distributed and specialized logic because different types of resources are placed in dedicated, independent columns. This means that IOBs are located in their corresponding columns, and not just in the periph- ery, and the number of IOBs only depends on the number of I/O pins the vendor decides the device to have. This actually applies to any resource: if more resources of a given type are to be included in a device, the number of columns of such type is just increased. Power supply and ground pins are distributed throughout the whole chip area, thus minimizing signal integrity problems. 

Column architectures are application oriented, because FPGAs with very different resources can be readily developed using chips with the same area and pin count, allowing the cost–performance trade-off to be optimized for each particular application. 

A column architecture specifically targeting high-frequency/bandwidth applications is shown in Figure 2.4. In it, flip-flops (“Hyper-Registers”) are placed in all interconnection segments and in all inputs of dedicated func- tional blocks, in addition to the usual locations in LBs and IOBs (as described in Section 2.3). 

The availability of these flip-flops throughout the entire device allows design techniques such as retiming and pipelining to be more efficiently implemented (Hutton 2015). The use of such techniques reduces signal delay times, in turn allowing higher operation frequencies to be achieved. In more “classical” architectures, the implementation of these techniques must be done using the flip-flops of the distributed logic, which usually implies that 

FIGURE 2.4 Altera’s HyperFlex architecture.

an advantage cannot be taken from most of the resources of the LBs used and that delays are also higher, resulting in less efficient solutions.