FONT SIZE : AAA
Unfortunately, there are differences between synthesis software packages and so care must be taken to ensure interoperability between packages, particularly in multiteam designs or when using third-party VHDL cores. The cores may have been synthesized using software different from the one you are using in your design flow, so the advertised synthesizable core may not always be synthesizable for you, in your design flow.
Because of this, it is usually a good idea to keep the VHDL as generic as possible and avoid using tricks of a particular package if you plan to deliver IP cores or use different tools. This may lead to slightly less compact VHDL, but the reliability of the VHDL will be greater, and potential problems (which could cause significant delays later in the design process, particularly in an integration phase) can be avoided.
One case is the use of different trigger variables in a process. For example, if there is a clock and a reset signal, or a clock and an enable signal, it is tempting to combine the logic into one expression such as:
1 if (clk’event and clk=’1’ and nrst =’0’) then
2 .
3 end if;
However, in some synthesis software this would cause an error. It is always preferable to separate these variables into nested if statements for three reasons:
1. The code will be more readable.
2. The chance of undefined logic states is reduced.
3. The synthesis software will not have a problem with your VHDL!
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Any -
RoHS: -
Manufacturer:Xilinx
Product Categories: Rangée de condensateur
Lifecycle:Obsolete -
RoHS:
Support
