How Does Configurable Logic Work?

First of all, it is important to highlight the intrinsic difference between programmable and (re)configurable systems. The “P” in FPGA can be mislead- ing since, although FPGAs are the most popular and widely used configu- rable circuits, it stands for programmable. Both kinds of systems are intended to allow users to change their functionality. However, not only in the context of this book but also according to most of the literature and the specialized jargon, programmable systems (processors) are those based on the execu- tion of software, whereas (re)configurable systems are those whose internal hardware computing resources and interconnects are not totally configured by default. Configuration consists in choosing, configuring, and intercon- necting the resources to be used. Software-based solutions typically rely on devices whose hardware processing structure is fixed, although, as dis- cussed in Chapter 3, the configurable hardware resources of an FPGA can be used to implement a processor, which can then obviously be programmed. The fixed structure of programmable systems is built so as to allow them to execute different sequences (software programs) of basic operations (instructions). The programming process mainly consists in choosing the right instructions and sequences for the target application. During execu- tion, instructions are sequentially fetched from memory, then (if required) data are fetched from memory or from registers, the processing operation implied by the current instruction is computed, and the resulting data (if any) are written back to memory or registers. As can be inferred, the hard- ware of these systems does not provide functionality by itself, but through the instructions that build up the program being executed. 

On the other hand, in configurable circuits, the structure of the hardware resources resulting from the configuration of the device determines the functionality of the system. Using different configurations, the same device may exhibit different internal functional structures and, therefore, different user-defined functionalities. The main advantage of configurable systems with regard to pure software-based solutions is that, instead of sequentially executing instructions, hardware blocks can work in a collaborative concur- rent way; that is, their execution of tasks is inherently parallel. 

Arranging the internal hardware resources to implement a variety of digi- tal functions is equivalent, from a functional point of view, to manufactur- ing different devices for different functions, but with configurable circuits, no further fabrication steps are required to be applied to the premanufac- tured off-the-shelf devices. In addition, configuration can be done at the user premises, or even infield at the operating place of the system. 

The beginning of reconfigurable devices started with programmable* logic matrices (programmable logic array [PLA] and programmable array logic [PAL]—whose basic structures are shown in Figure 1.4), where the connectivity of signals was decided using arrays of programmable con- nections. These were originally fuses (or antifuses † ), which were selectively either burnt or left intact during configuration. 

FIGURE 1.4 Programmable matrices: (a) PLA; (b) PAL.

* At that time, the need for differentiating programmability and configurability had not yet

been identified.

† The difference between fuses and antifuses resides in their state after being burnt, open or

short circuit, respectively.

In programmable matrices, configuration makes the appropriate input signals participate in the sums of products required to implement differ- ent logic functions. When using fuses, this was accomplished by selectively overheating those to be burnt, driving a high current through them. In this case, the structural internal modifications are literally real and final, since burnt fuses cannot be configured back to their initial state. 

Although the scale of integration of fuses was in the range of several micrometers (great for those old days), CMOS integration was advancing at a much faster pace, and quite soon, new configuration infrastructures were developed in the race for larger, faster, and more flexible reconfigu- rable devices. Configuration is no longer based on changes in the physical structure of the devices, but on the behavior regarding connectivity and functionality, specified by the information stored in dedicated memory elements (the so-called configuration memory). This not only resulted in higher integration levels but also increased flexibility in the design process, since configurable devices evolved from being one-time programmable to being reconfigurable, which can be configured several times by using eras- able and reprogrammable memories for configuration. Nowadays, a clear technological division can be made between devices using nonvolatile con- figuration memories (EEPROM and, more recently, flash) and those using volatile configuration memories (SRAM, which is the most widely used technology for FPGA configuration). 

Currently, programmable matrices can be found in programmable logic devices (PLDs), which found their application niche in glue logic and finite- state machines. The basic structure of PLDs is shown in Figure 1.5. In addition to configuring the connections between rows and columns of the program- mable matrices, in PLDs, it is also possible to configure the behavior of the macrocells. 

The main drawback of PLDs comes from the scalability problems related to the use of programmable matrices. This issue was first addressed by includ- ing several PLDs in the same chip, giving rise to the complex PLD concept. However, it soon became apparent that this approach does not solve the scal- ability problem to the extent required by the ever-increasing complexity of digi- tal systems, driven by the evolution of fabrication technologies. A change in the way configurable devices were conceived was needed. The response to that need were FPGAs, whose basic structure is briefly described in the following.* 

Like all configurable devices, FPGAs are premanufactured, fixed pieces of silicon. In addition to configuration memory, they contain a large number of basic configurable elements, ideally allowing them to implement any digi- tal system (within the limits of the available chip resources). There are two main types of building blocks in FPGAs: (relatively small) configurable logic circuits spread around the whole chip area (logic blocks [LBs]) and, between them, configurable interconnection resources (interconnect logic [IL]). 

FIGURE 1.5 (a) Basic PLD structure; (b) sample basic macrocell.

The functionality of the target system is obtained by adequately configur- ing the behavior of the required LBs and the IL that interconnects them, by writing the corresponding information in the FPGA’s internal configuration memory. The information is organized in the form of a stream of binary data (called bitstream) coming out from the design process, which determines the behavior of every LB and every interconnection inside the device. FPGA configuration issues are analyzed in Chapter 6. 

A most basic LB would consist of the following: 

• A small SRAM memory (2 n × 1, with a value of n typically from 4 to 6) working as a lookup table (LUT), which allows any combinational function of its n inputs to be implemented. A LUT can be thought of as a way of storing the truth table of the combi- national function in such a way that, when using the inputs of that function as address bits of the LUT, the memory bit storing the value of the function for each particular input combination can be read at the output of the LUT. 

• A flip-flop whose data input is connected to the output of the LUT.

• A multiplexer (MUX) that selects as output of the LB either the flip-flop output or the LUT output (i.e., the flip-flop input). In this way,

depending on the configuration of the MUX, the LB can implement either combinational or sequential functions.

• The inputs of the LB (i.e., of the LUT) and its output (i.e., of the MUX), connected to nearby IL.

In practice, actual LBs consist of a combination of several (usually two) of these basic LUT/flip-flop/MUX blocks (which are sometimes referred to as slices). They also often include specific logic to generate and propagate carry signals (both inside the LB itself and between neighbor LBs, using local carry-in and carry-out connections), resulting in the structure shown in Figure 1.6. Typically, in addition, the LUTs inside an LB can be com- bined to form a larger one, allowing combinational functions with a higher number of inputs to be implemented, thus providing designers with extra flexibility. 

In addition, current FPGAs also include different kinds of specialized resources (described in detail in Chapters 2 through 5), such as memories and memory controllers, DSP blocks (e.g., MAC units), and embedded pro- cessors and commonly used peripherals (e.g., serial communication inter- faces), among others. They are just mentioned here in order for readers to understand the ever-increasing application scope of FPGAs in a large variety of industrial control systems, some of which are highlighted in Section 1.5 to conclude this chapter. 

FIGURE 1.6 Example of two-slice LB and its connection to IL.