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One of the biggest challenges for a new prototyping team is the inclusion of IP, especially high-speed peripheral IP. Third-party IPs are often provided without source code, so they cannot be synthesized as part of the RTL and an alternative must be found. This could be a netlist in the SoC library or pre-mapped to FPGA elements. It could also be an external testchip or an encrypted version of the RTL.
All of these forms of the IP can be used but we should not lose sight of the purpose which is not to verify the IP; that should have been guaranteed already. The reason to model the IP is so we do not leave a hole in the design. Having the IP present in some form allows us to validate the rest of the hardware and especially the software running upon it.
The authors gratefully acknowledge significant contribution to this chapter from
Spencer Saunders of ARM, Cambridge
Antonio Costa of Synopsys IP Group
Peter Gillen of Synopsys IP Group
Torrey Lewis of Synopsys IP Group
David Taylor of Xilinx, Edinburgh
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