Hybrid FPGA–FPAA Solutions

From previous sections, it is clear that, compared with logic resources, ana- log resources available in FPGAs are still quite limited. However, there is a trend for FPGA vendors to include in their most current devices an increas- ing number of analog blocks of increasing complexity. 

For more than 20 years now, researchers and vendors have explored the feasibility of developing analog reconfigurable devices. Currently, commercial solutions already exist that combine configurable ana- log and digital resources. These are the so-called FPAAs, conceptually equivalent to FPGAs but oriented to analog applications. They consist of a set of analog blocks supporting a certain degree of configurability through the use of configurable analog blocks and digitally configurable interconnections to connect analog blocks among themselves and to I/O pins. Examples of such devices are Anadigm AN13x and AN23x families (Anadigm 2006). 

Taking into account that the digital part of “pure” FPAAs is limited to inter- connect and configuration resources, as well as to resources for the imple- mentation of simple transfer functions, the detailed analysis of these devices is beyond the scope of this book. However, intermediate solutions between FPGAs and FPAAs exist. Such hybrid devices are available in Cypress PSoC 1, PSoC 3, PSoC 4, and PSoC 5LP family series (Cypress 2015). As the term PSoC suggests, these devices include embedded hardware processors, so they might have been analyzed in Chapter 3. However, considering that their most distinctive features are related to their analog part, we have decided to describe them here. 

Figure 5.9 shows the architecture of the CY8C58LP family (PSoC 5LP series). It consists of three main blocks: Processor System, Digital System, and Analog System. The Processor System includes, among other modules, 

• A 32-bit ARM Cortex-M3 processor, capable of operating at up to 80 MHz (1.25 DMIPS/MHz) 

• A Nested Vectored Interrupt Controller (NVIC) for fast interrupt handling, supporting up to 16 system exceptions and 32 interrupts 

• Debug and trace modules accessible through JTAG or Serial Wire Debug interfaces 

FIGURE 5.9 Architecture of the CY8C58LP family.

• Up to 256 kB of flash memory, 2 kB of EEPROM, and 64 kB of SRAM 

• An external memory interface 

• DMA and cache controllers 

Connection of the Processor System with other parts of the device is made through a peripheral hub based on AMBA multilayer AHB interconnection scheme (described in Section 3.5.1.2). The digital system consists of three main blocks: 

1. An array of configurable logic blocks, called Universal Digital Blocks (UDBs) 

2. Hard peripherals, including serial communication interfaces (CAN, USB, and I 2 C), timers, counters, and PWMs 

3. A communication interface (digital system interface [DSI]) to inter- connect reconfigurable logic, I/O pins, hard peripherals, interrupts, and DMA circuitry 

Each UDB includes two PLDs (configurable structures much simpler than those in most current FPGAs, as introduced in Section 1.4), a datapath, and interconnection resources. 

The datapath inside each UDB consists of an 8-bit single-cycle ALU and logic resources for comparison, shifting, and condition generation. It sup- ports condition and signal propagation chains (e.g., carries) for the efficient implementation of arithmetic and shift operations. The datapath and the PLDs combine to build a UDB, and UDBs combine to build a UDB array. 

Some devices in the CY8C58LP family also include a digital filter hardware block (DFB) as part of the digital system. The DFB includes a multiplier and an accumulator supporting 24-bit single-cycle MAC operations. To the best of authors’ knowledge, no similar blocks exist in other devices to relieve the ARM Cortex-M3 core of this kind of highly bandwidth-consuming tasks. 

Finally, the configurable analog system, which clearly separates these devices from any other current ones and whose structure is shown in Figure 5.10, consists of the following elements: 

• A delta–sigma ADC whose default configuration is 16-bit resolu- tion and 48 ksps, but is capable of also operating in other modes: 20, 12, or 8 bits and 187 sps, 192 ksps, or 384 ksps. It has a differen- tial input, supports single and continuous sampling, and conversion start can be controlled either by software (by writing in a register) or hardware (through an external signal). 

• Two 12-bit, 1 Msps SAR ADCs with single-ended or differential input. 

• Four 8-bit DAC with voltage or current output. They support conver- sion rates up to 8 Msps for current output and 1 Msps for voltage output. 

• Four analog comparators, whose outputs can be connected to four 2-input LUTs (allowing simple functions to be implemented) and, from them, to the digital system. 

• Four programmable switched capacitor/continuous time (SC/CT) blocks, including one operational amplifier and a resistor network. With these elements, functionalities such as programmable gain amplifiers, transimpedance amplifiers, up/down mixers, S&H, and first-order analog to digital modulators, among others, may be built. 

• Four general-purpose operational amplifiers supporting any voltage amplifier or follower configuration using either internal or external signals. 

• A configurable interface for LCD displays, compatible with a wide variety of LCD displays. 

• A capacitive touch sensing interface (CapSense subsystem in Figure 5.10) enabling capacitive measurements from devices such as proximity sensors, touch-sense buttons, and sliders. 

FIGURE 5.10 Analog system of CY8C58LP family.

• A temperature sensor to monitor internal device temperature. 

• Internal high-precision reference voltages. 

• Configurable resources to interconnect the different analog blocks as well as connect them with GPIOs. Interconnection resources are structured in global and local buses, MUXes, and switches. 

For generation, synthesis, and distribution of clock signals, CY8C58LP devices include internal oscillators; specific (separate) clock frequency divid- ers for the digital, analog, and processor parts; and a fractional PLL with a working range from 24 to 80 MHz. 

Cypress provides the PSoC Creator tool to support design of these devices. It eases configuration of both analog and digital interconnects, includes a library of predefined functions, and generates API interface libraries to set up communications between the process system and all other blocks in the device.