Analog Data Acquisition and Processing Interfaces

Analog resources in Microsemi SmartFusion FPGAs (Microsemi 2014a) are more complex than those described so far. They build a subsystem for ana- log signal acquisition and processing, called Analog Compute Engine (ACE), which consists of three blocks (Figure 5.6): analog front-end interface, Sample Sequencing Engine (SSE), and Post-Processing Engine (PPE). 

FIGURE 5.6 ACE analog subsystem from Microsemi SmartFusion family.

The analog front end includes signal conditioning circuits with S&H, ana- log MUXes, ADCs, and DACs. ADCs are SAR ones, with configurable reso- lution up to 12 bits (8, 10, or 12 bits). It supports simultaneous sampling of several ADCs. Reference voltage can be internal or external, in the 0–2.56 V range. To extend input voltage range, a prescaler is available with up to four different ranges. 

Additional resources making a significant difference from other solu- tions are 24-bit delta–sigma DACs (as many as ADCs), current monitors based on differential-input, fixed-gain (50) amplifiers, temperature sen- sors, and high-speed analog comparators with configurable hysteresis thresholds. Single-ended analog inputs and outputs are multiplexed and demultiplexed, respectively. A very useful feature of these devices is that the embedded microcontrollers they include are equipped with dedi- cated interfaces to the analog circuitry, which in this regard acts as a slave peripheral of the microcontroller. Moreover, access and control of the ana- log resources can also be made from distributed logic without the need for using the microcontroller. 

Given the complexity of the analog front end, a simple microcontroller (SSE) is available for configuring the parameters and operating modes of the different analog modules as well as for defining the sampling and conversion sequences of the input and output analog channels. Sampling sequences, resolution, and sampling times can be independently configured for each ADC. Simultaneous analog-to-digital conversion is supported as well as simultaneous updating of DAC outputs. 

The PPE block is in charge of processing the signals from the ADCs. It uses FIFO memories to store data coming from each ADC and an ALU capable of performing calibration, threshold comparison, or other linear transforms. It can also be configured as a MAC unit, allowing low-pass filters to be implemented. 

Thanks to the availability of SSE and PPE, there is no need to use embed- ded processors or distributed logic to perform the complex control and pro- cessing tasks associated with the analog part of the devices. Anyway, to facilitate high-level tasks, both SSE and PPE can generate interrupt requests to flag events related to calibration, the operation of the ADCs or the com- parators, as well as general-purpose SSE events, or threshold comparison– related PPE events. 

Another example of relatively complex mixed-signal FPGAs is the Microsemi Fusion family (Microsemi 2014b), whose architecture is shown in Figure 5.7. It includes up to 30 multiplexed analog inputs, a SAR ADC with configurable resolution (8, 10, or 12 bits) and sampling frequency up to 600 ksps, as well as temperature, voltage, and current sensors, and (as a 

FIGURE 5.7 Architecture of Microsemi Fusion family.

significantly distinctive feature) up to 10 MOSFET gate driver outputs to control high-voltage external FETs. Same as other solutions, the reference voltage can be internal (2.56 V) or external (up to 3.3 V). 

As shown in Figure 5.7, analog I/O resources are grouped in the so- called analog quad blocks, whose internal structure is shown in Figure 5.8. Each block includes three analog inputs (AV, AC, and AT) and a gate driver output pad (AG). They can be configured to operate in different modes, such as digital inputs, temperature or current monitor, or analog inputs with pres- caler. Prescalers support different scaling factors to adapt to different ranges of positive (0–12 V) or negative (−12 to 0 V) input voltage. 

Fusion devices include a TSD connected to channel 31 of the analog MUX, aimed at measuring internal chip temperature. In addition, the AT input of each analog quad can be connected to an external tempera- ture sensor. 

Current monitoring is carried out by connecting an external resistor of known value (typically less than 1 Ω) between two adjacent analog inputs 

FIGURE 5.8 Block diagram of the analog quad blocks.

(AV and AC) and measuring the voltage drop between them. Operational amplifiers are available to amplify this voltage for improved current measurement accuracy.