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As mentioned in section 10.2, the only form of IP available in some cases is an external test chip or hard IP. There are many reasons why we would want to use a hard IP block alongside our FPGAs, some of which may be forced upon us, for example, the RTL is not available or not supported by the IP vendor for external usage.
The most common hard IP blocks found in prototypes are CPU cores and standard bus interfaces using PHY, including Ethernet, USB, PCI/PCI-X/PCIe and memory interfaces such as DDR2. Many vendors offer their IP as hard macros preimplemented by various semiconductor partners and as end users we might choose a hard IP which most closely reflects our final silicon usage.
A good by product of using test chips and external hard IP is that they free-up FPGA resources. These are then freed up for other uses or left unused, lowering the device utilization and therefore decreasing runtime and potentially increasing performance. We should note that the FPGA resources required for large IP blocks such as DSPs or processor sub-systems could easily consume a whole FPGA or even multiple FPGAs. In the latter case the cost and performance impact of splitting IP across multiple FPGAs might be too high, especially if we do not have intimate visibility of the internal workings of the IP. In these cases, it would make sense to use an external hard IP or test chip, accepting the limitations this may impose compared to the effort required to develop a larger multi-FPGA solution. These are amongst the decisions to be made in the early stages of the project (see chapter 4).
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: CPLDs
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Manufacturer:Xilinx
Product Categories: Embedded - CPLDs (Complex Programmable Logic Devices)
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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