ADC Blocks

Figure 5.1 shows the mixed-signal FPGA architectures of Altera MAX 10 and Xilinx 7 Series devices. They include up to two* 12-bit Successive 

Approximation Register (SAR) ADCs and share the following features: 

• Maximum sampling rate: 1 Msps (minimum conversion time 1 μs). 

• Single clock cycle conversion. 

• Several multiplexed input channels (up to 18 in Altera devices with 2 ADCs and up to 17 in Xilinx ones). Channel 0 is a dedicated analog input, whereas all others are dual function (i.e., they can be config- ured as either analog inputs or general-purpose digital I/O pins). 

FIGURE 5.1 (a) ADC hard block from Altera’s MAX 10 family and (b) XADC block from Xilinx 7 Series.

* All Xilinx 7 Series devices include two ADCs, whereas Altera’s MAX devices may contain one or two, depending on the particular device.

• Support both single-ended and differential input signals. 

• Support different operation modes, such as continuous sampling, conversion triggered by a specific event, and independent or simul- taneous sampling (in devices with two ADCs). 

• Support internal or external voltage references. Since ADC accuracy strongly depends on reference voltage, any ripple or noise affecting it negatively impacts conversion quality (e.g., conversion gain or sig- nal-to-noise ratio). Since the internal voltage reference is usually the very supply voltage of the ADC (producing ratiometric conversion results), vendors recommend the use of external voltage references, for which it is easier to ensure better accuracy and lower tempera- ture drift. 

• Each ADC has an associated sample-and-hold (S&H) circuit or track- and-hold amplifier to ensure proper conversion. Some devices sup- port configurable settling time. 

On the other hand, there are differences in input voltage ranges and output configurations between the two families. In Altera MAX 10 devices, input voltages can be in the 0–2.5 or 0–3.3 V ranges, depending on the supply voltage, and the transfer function is unipolar (Figure 5.2). Input voltages are in the 0–1 V range in Xilinx 7 Series devices, whose transfer function can be unipolar or bipolar, in 2’s complement (Figure 5.3). 

FIGURE 5.2 Unipolar ADC transfer function in Altera devices.

FIGURE 5.3 Bipolar ADC transfer functions in Xilinx 7 Series devices.

As can be clearly noticed in Figure 5.1, both hardware architectures are very similar. They consist of a set of input channels (coming from either external pins or internal signals), connected to the ADCs through multiplex- ing logic and S&H circuits, as well as of additional logic resources, aimed at configuring and controlling the ADCs and storing the results. For instance, control registers at the bottom of Figure 5.1 are used for storing the con- figuration parameters of the analog block, whereas status registers store con- verted data. 

Control logic for hardware specialized analog blocks is implemented in the FPGA fabric. Specific communication resources are available for this pur- pose. For instance, the DRP (Dynamic Reconfiguration Port) in Figure 5.1b is a 16-bit synchronous read/write port, which enables access to control and status registers from the FPGA fabric. These registers are also accessible from the JTAG interface of the FPGA. 

Specific IP cores are available for both MAX 10 and 7 Series devices to inter- act with the respective analog blocks. They are parameterizable soft control- lers implementing several different predefined configurations and operating modes. They allow on-chip ADCs to be instantiated in a design, as well as clock signals and reference voltages to be configured, the input channel to be dynamically selected, maximum and minimum data values to be defined (and violation notifications to be generated if these are exceeded), and the whole data acquisition process to be managed in a way totally transparent to the designer, who does not need to care about low-level details. 

FIGURE 5.4 Common architecture of the control logic for analog resources in mixed-signal FPGAs.

Figure 5.4 shows the minimum set of resources required by the control logic: 

• A control circuit (finite state machine), in charge of generating configuration and sampling signals (address, data, and transfer signals for configuration registers, start and end of conversion signals, handshake signals, etc.) so that they follow the required sequences and comply with the timing requirements specified by the vendor 

• A sequencer to define the sampling sequence of input channels 

• Memory resources to store data 

• Clock and synchronization circuits 

The control circuit and the sequencer are implemented in FPGA distrib- uted logic, whereas acquisition memory may be implemented using either embedded or external memory blocks. Clock signals are generated using dedicated blocks (such as PLLs or DLLs) to ensure their stability and reduced skew. 

These analog blocks support very diverse operating modes. In MAX 10 devices: 

• It is possible to configure the order in which a set of input channels are sampled (i.e., an acquisition sequence). Acquisition sequences can be configured in single-trigger or continuous mode. 

• In devices with two ADCs, each of them may be independently con- figured to have a different acquisition sequence, and acquisitions may be synchronous (using the same clock for both ADCs) or asyn- chronous (using different clock signals). In addition, simultaneous acquisition is supported in cases where the relative phase of input signals must be kept unchanged. Simultaneous acquisition can only be implemented using the dedicated analog inputs ( channel 0 of each ADC, as mentioned earlier), whose package routings are matched. 

Both single-channel acquisition and acquisition sequences (automatic chan- nel sequencer) are also possible in 7 Series devices, which also support single-trigger (single-pass mode) and continuous mode. Acquisitions in each ADC may be independent (one ADC acquires internal signals and the other external ones) or simultaneous. Differently from MAX 10 devices, in simul- taneous acquisition mode, all external analog channels can be used. Since there are up to 16 dual-function pins (channels) available, up to eight simul- taneous acquisition channels may be defined. 

More specifically, in single-pass, automatic channel sequencer and continuous sequence modes, one ADC (“A”) samples input signals (from temperature and voltage sensors) and the dedicated analog input, whereas the second ADC (“B”) handles all other external channels. In simultane- ous sampling mode, each ADC is connected to eight external signals, which are sampled in pairs (both ADCs operate in parallel), but it is also possible to include internal signals in the sampling sequence, associated with ADC “A” (in this mode, when sampling internal signals, ADC “B” is inactive). Finally, in independent ADC mode, ADC “A” samples internal signals, whereas ADC “B” samples the dedicated analog input and all other exter- nal channels. 

Analog blocks in 7 Series devices also support external MUX mode (Figure 5.5), where (as the name indicates) an external input MUX (connected to the dedicated analog inputs) is used for channel multiplexing (channel selection logic is still generated by the embedded analog block). This is a use- ful option for designs where not enough I/O pins remain available once the digital logic has been defined. It has to be noted that the 17 input channels (differential inputs) supported by the analog block would actually consume 34 I/O pins. 

Following the general philosophy behind configurable devices, ana- log resources in mixed-signal FPGAs are usually highly configurable. In addition to the aforementioned operating modes, other functionalities and parameters may be configured, even at run time. For instance, in 7 Series devices, each analog input can be independently configured to operate in unipolar or bipolar mode (to reduce common-mode noise), the output digital value may be obtained as the direct result of a single conversion or as the average of a set of samples (16, 64, or 256), and each ADC may be digitally calibrated to reduce gain and offset errors. Calibration is performed by con- necting the ADC input to a known voltage, computing gain and offset errors, and generating the corresponding correction coefficients. Users can choose whether or not correction coefficients are applied by enabling or disabling the calibration option, respectively. 

FIGURE 5.5 External (a) MUX and (b) simultaneous sampling modes.