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Home > FPGA Technical Tutorials > Designing with Xilinx FPGAs Using Vivado > Vivado Design Tools > Overview of Vivado GUI

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Overview of Vivado GUI

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This section provides a high level overview of the Vivado GUI and some recom- mendation for fi rst-time users. Vivado is designed based on a concept of layered complexity. This means using the tool for common tasks and designs is made as automated and easy as possible without having to have detailed knowledge of the tool. However, once you get more familiarized with the tool and want to use advanced features to control your design fl ows in a customized manner, Vivado allows you with higher control with fi ner granularity. 

Vivado GUI and project- based mode is highly recommended for fi rst-time users or those who want to get quickly up and running. Using the GUI makes it easy to use the various wizards (like New Project wizard) to get started. First-time users can leave all settings at default and let the tool decide best automatic options. There are several example projects included with Vivado which you can readily open and use to try out the design fl ows. If you want to try your own design, the only two minimum required pieces of input are an HDL fi le to describe the design and a constraint fi le to specify the timing intent and pin mapping of the in/out signals to specifi c FPGA pins. 

Figure 2.1 shows the screenshot of the Vivado GUI with some of the key areas highlighted: 

1. This area is called the Flow Navigator . It provides easy, single click access to the common design fl ow steps and confi guration options.

2. This area shows the sources in the design. The fi rst tab here shows a graphical view of the sources with modules and instance relationships. The other tabs in this area show other key aspects of design sources.

3. This area shows the properties of the items selected in the GUI.

4. This area shows the Tcl console in the GUI as well as various reports and design run related details.

5. This area shows the built-in text editor, information related to project summary, etc.

6. This is a view of a design open in the GUI, which is key to all the design implementation steps.

Overall organization of Vivado GUI.png

Fig. 2.1 Overall organization of Vivado GUI

Starting in the GUI and following the wizards make it easy to get started with the Vivado design fl ow. At the same time, as the various operations are being performed in the GUI, Vivado generates equivalent Tcl commands for those operations in the Tcl console area, as well as in the journal fi le as mentioned in Sect. 2.2 . Using these Tcl commands, you can later customize the fl ow or build other similar fl ows. 

  • XC4VLX25-12FFG668C

    Manufacturer:Xilinx

  • FPGA Virtex-4 LX Family 24192 Cells 90nm Technology 1.2V 668-Pin FCBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

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  • XC4VLX40-10FFG668I

    Manufacturer:Xilinx

  • FPGA Virtex-4 LX Family 41472 Cells 90nm Technology 1.2V 668-Pin FCBGA
  • Product Categories: FPGAs (Field Programmable Gate Array)

    Lifecycle:Active Active

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  • XC17V01VO8C

    Manufacturer:Xilinx

  • PROM Parallel/Serial 1.6M-bit 3.3V 8-Pin TSOP
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    Lifecycle:Obsolete -

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  • XC17V02PC44C

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  • PROM Parallel/Serial 2M-bit 3.3V 44-Pin PLCC
  • Product Categories: Memory - Configuration Proms for FPGA's

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XCR3384XL-FT256C

    Manufacturer:Xilinx

  • Xilinx BGA
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    Lifecycle:Any -

    RoHS: -

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