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The structure of a basic sample hardware 18-bit multiplier capable of performing both signed and unsigned operations is shown in Figure 4.2. In it, input and output registers allow (optionally) the operands and the result (36-bit, full-precision) to be memorized. In this way, for instance, the data and coefficients of a filter could be stored. Another advantage of these regis- ters is for the straightforward implementation of efficient pipelining struc- tures, taking advantage of the short delays associated with the dedicated connections inside the multiplier.
FIGURE 4.2
Embedded multiplier from Xilinx Spartan-3 devices. (From Xilinx, Spartan-3 Generation FPGA
User Guide: Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families: UG331 (v1.8), 2011.)
MAC units can be obtained by combining embedded multipliers, LBs (where additions may be implemented), and embedded memory (where input data and results are stored). This is the reason why embedded multipliers are usu- ally placed adjacent to memory blocks, so routing among them is simplified, resulting in more efficient designs. Although 18 bits is not a usual data width in digital systems (it is not a power of 2), 18-bit multipliers are present in many FPGAs because they match a typical data width of memory blocks. Embedded memory data widths in FPGAs are usually multiples of 9, so information can be stored as sets of eight data bits plus one parity bit. However, if no data integ- rity checks are required, data can be stored in all nine bits. Therefore, it makes sense that arithmetic operators work with data widths that are multiples of 9.
Multipliers have associated resources for chain interconnection between adjacent blocks. In this way, it is possible to extend the number of bits of the operands or to build shift registers (which are usually required in DSP appli- cations), by connecting input registers in a chain.
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