System Level Functions

In addition to the SoC and programmable logic array, FPGAs include system level functions for confi guring and monitoring FPGAs.

System Monitor

For industrial and embedded applications, it is desirable to be able to monitor the voltage of system power supplies and various analog signals as well as the internal temperature of the FPGA. This allows the FPGA to detect if the power rails are within specifi ed tolerance and allows the FPGA to know it is operating legally. For this reason and also for security reasons, FPGAs incorporate a small multichannel ADC (analog-to-digital converter). Chapter 16 covers more on system monitor.

Fabric Power Management

Before SoCs were introduced, FPGAs operated on a single power domain. Typicallyseveral voltages are required for the FPGA, the logic power supply, the auxiliarypower supply, and the I/O power supplies. The FPGA fabric supports several featureswhich allow the user to manage and minimize system power. FPGA fabric powerconsists of two types of power—static power which exists even if the device is notoperating and dynamic power which is a function of clock rates and data activity.Static power is quite low at low temperatures but can rise to signifi cant levels at maxi-mum die temperatures. Additionally some speed and temperature grades have lowerstatic power than others. The -2L speed grade is designed to operate at lower voltagelevels enabling lower system power. The user has some fl exibility to manage power bythrottling fabric clocks if idle and by lowering die temperature using fan control.

SoC Device Power Management

The SoC devices introduce some additional fl exibility in power management if the application allows for sometimes running in reduced functionality or idle modes. The Zynq-7000 devices support independent PS ( processing system ) and PL (pro- grammable logic) power domains. Thus, if the PL is idle, its power supply can be removed. The MPSoCs support even fi ner-grained power domains and can be placed into low-power modes with only the R5s operating. This allows system power as low as 50 mW to be achieved for low-performance modes. Normal operation of the SoC would be in the 1–3 W range and the PL could be in the 2–20 W range.

Confi guration

Both the PS SoC and the PL require confi guration data to function. For the PS this is boot code, and for the PL, it is called the bitstream data. FPGAs will commonly include a dedicated block to confi gure the FPGA from various sources of bitstream data. Xilinx supports boot over JTAG, over a dedicated serial or parallel interface and from dedicated fl ash memory devices. In the SoC devices, confi guration is supported by a confi guration controller in the SoC. Optionally UltraScale devices can be booted over a PCIe interface, eliminating the cost of local fl ash storage and simplifying system level confi guration data management.

Security

FPGA security is a relatively new concern, but modern devices contain multiple security features which are used to decrypt, authenticate, and monitor confi guration data. Encryption is used to obscure the confi guration data which is stored in external memory devices. This is valuable to protect user IP (intellectual property) as well as to provide protection for passwords and keys embedded in the confi guration data. FPGAs now store one-time programmable encryption key (of up to 256 bits) which is used to decrypt confi guration data on the fl y.

Today it is critical for system integrity to check confi guration data for correct- ness before loading into the PL and SoC. The confi guration controller optionally does this by fi rst checking to see if the boot code or bitstream can be authenticated. The MPSoC devices support authentication of up to 4 K bits in hardware. If an authentication fails, the device cannot be booted. The bitstream is authenticated against a decryption key stored in external memory.

Additional features of MPSoC devices include tamper detection circuitry with clock, power, and temperature monitoring. This can be used to deter attacks based on operating the device outside of its legal operating conditions.

Within the Zynq UltraScale + PS , hardware is used to isolate various parts of the sys- tem. This can prevent the application code from overwriting the secure real-time code.

Safety

FPGAs are physical devices which are specifi ed to operate under specifi c voltage and temperature conditions. They have a designed lifetime of 10 years of opera- tion after which they may fail in various ways. During normal operation cosmic rays and alpha radiation from radioactive trace elements can upset device regis- ters. For these reasons circuitry has been built into the FPGA to monitor confi gu- ration data changes due to upset or other effects. The FPGA confi guration data is monitored for a digital signature. If this changes unexpectedly, a signal is raised which can reset the FPGA. Memories are particularly sensitive to upset, and all PL block RAMs and the large PS memories have added parity bits to detect a single event upset.

Debug

Getting a large FPGA to production is a challenging effort. In order to facilitate debugging a dedicated JTAG interface is provided on the FPGA and PS. This inter- face has access to the FPGA confi guration system and the PS memory map. It can be used to download code and to test system level I/O interfaces. Cross-trigger circuitry is available to debug SoC software and PL hardware simultaneously. The PS also includes support for standard ICE debugging pods.

Performance Monitoring

The MPSoC includes a number of performance monitors which can check and measure traffi c on the AXI interconnect. For the PL these performance monitoring blocks can be implemented in soft logic to monitor PL AXI events.

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