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In this chapter we have covered the bulk of the tasks we undertake n order to overcome the third law of prototyping. We have used a number of techniques to remove or at least neutralize elements of the SoC design which would not have worked as they are in FPGA. We hope that we have not discouraged readers from starting because even the most pathologically FPGA-hostile design can eventually be mapping onto an FPGA board.
Successful SoC prototyping demands a good understanding of FPGA technology and implementation tools, but most of all, we need to recognize which parts of the design will best respond to one or other of the above techniques.
The authors gratefully acknowledge significant contributions to this chapter from:
Steve Ravet of ARM, Austin
Joel Sandgathe of Microvision, Seattle
Pete Calabrese of Synopsys, Boston
Ramanan Sanjeevi Krishnan of Synopsys, Bangalore
Nithin Kumar Guggilla of Synopsys, Bangalore
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