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Handling RAMs

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Memory is the most common SoC element that requires some manipulation to be  FPGA-ready. We will focus now on RAM in particular and consider other types of  memory later. 

We have seen in section 7.5.5 that RAM can be described behaviorally in RTL and  then inferred by FPGA synthesis into the correct FPGA memory elements.  Unfortunately, SoC synthesis tools do not handle memory in the same way, and  instead they are instantiated as black boxes in the RTL. Various views, such as  functional behavior and physical layout, are used to “fill” the black box later in the  SoC verification and implementation flows.  

These various views of the memory are often automatically created and  parameterized by a generator such as the coreConsultant from Synopsys or Custom  Touch Memory Compilers from Virage Logic. The SoC team will be familiar with  these types of tools and use them to generate very sophisticated memories,  optimized for the SoC design. In an ideal world, the FPGA synthesis would  recognize the black box as the output from a particular memory generator and  automatically replace it with an equivalent FPGA view. However, there are a large  number of possible memory configurations, as can be seen in Table 16, and the  synthesis would need to infer the functionality of each of them with only the  reference of the black box name from external library as a guide.

Examples of the wide range of RAMs in use in SoC designs.png

Maintaining a cross-reference of all possible SoC memories from all possible  generators to their closest FPGA equivalent would not be productive and typically  yields non-optimal results. Instead we focus on the specific RAMs in the SoC  (which will be a small subset of the overall range of possible configurations) and  create optimized replacements only for them.  Some help can be offered by the memory generator tools and memory IP developers  themselves and some do indeed generate FPGA equivalent views for use by  prototypers. In an ideal world our SoC team will have chosen their RAM for exactly  that reason, but in most cases we need to consider how we can replace an SoC RAM  with the FPGA equivalent.


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