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Once you’ve decided on a particular FPGA component for your design, one final decision is the speed grade of this device. The FPGA vendors ’ traditional pricing model makes the performance (speed grade) of a device a major factor with regard to the cost of that device.
—Technology Trade-offs—
As a rule of thumb, moving up a speed grade will increase performance by 12 to 15 percent, but the cost of the device will increase by 20 to 30 percent. Conversely, if you can manipulate the architecture of your design to improve performance by 12 to 15 percent (say, by adding additional pipelining stages), then you can drop a speed grade and save 20 to 30 percent on the cost of your silicon (FPGA).
If you are only contemplating a single device for prototyping applications, then this may not be a particularly significant factor for you. On the other hand, if you are going to be purchasing hundreds or thousands of these little rascals, then you should start thinking very seriously about using the lowest speed grade you can get away with.
The problem is that modifying and reverifying RTL to perform a series of what-if evaluations of alternative implementations is difficult and time consuming. (Such evaluations may include performing certain operations in parallel versus sequentially, pipelining portions of the design versus nonpipelining, resource sharing, etc.) This means that the design team may be limited to the number of evaluations it can perform, which can result in a less-thanoptimal implementation.
As discussed in Chapter 6, one alternative is to use a pure untimed C/C ++ -based flow. Such a flow should feature a C/C ++ analysis and synthesis engine that allows you to perform microarchitecture trade-offs and evaluate their effects in terms of size/are and speed/clock cycles. Such a flow facilitates improving the performance of a design, thereby allowing it to make use of a slower speed grade if required.
On the bright side, once a design team has selected an FPGA vendor and become familiar with a product family, it tends to stick with that family for quite some time, which makes life (in the form of the device selection process) much easier for subsequent projects.
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