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Home > FPGA Technical Tutorials > Designing with Xilinx FPGAs Using Vivado > State-of-the-Art Programmable Logic > Application Level System Architectures

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Application Level System Architectures

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The above applications in turn identify the need for the following system level usage, which might be applicable in multiple markets.

Glue Logic and Custom Interface IP

This was the original use case for early FPGAs. Typically the FPGA is used to interface a processor IC to a variety of I/O devices and memory-mapped devices. This use case requires low-cost FPGAs with plentiful I/O. Key features are combi- natorial programmable logic nets, IOBs, and internal registers. 

Often an application will require a custom interface such as an industrial inter- face or perhaps multiple interfaces such as USB. If these interfaces are not available in the user’s SoC, they can be implemented in a companion FPGA. 

Communications Switch

Multiple interfaces of various standards and performance levels such as 10G Ethernet are connected together via an FPGA implemented switch. These switches are common in Internet, industrial, and video networks.

I/O Stream Processing

FPGAs are ideal devices to connect to high-bandwidth real-time I/O streams such as video, radio, radar, and ultrasound systems. Often the system is used to reduce the high-native bandwidth of the I/O stream to levels manageable for a processor. For instance, a radio front end may sample A/D data at 1 GHz but after down con- version produces a more moderate rate of 10 MB/s. Conversely lower-bandwidth data may be up converted to a high-bandwidth I/O stream. Another example is a video system with a frame buffer which may be updated infrequently, but the video output stream is a real-time high-bandwidth stream. 

Software Acceleration

An emerging FPGA system architecture allows software to be accelerated either with a companion FPGA attached to a high-end CPU or with an SoC-based FPGA such as the Zynq UltraScale + MPSoC (MPSoC). This acceleration will usually be accompanied by a signifi cant power reduction per operation. In this use case, the FPGA is programmed on the fl y to implement one or more cascaded software func- tion calls on data in memory. The FPGA gates are compiled or derived from a com- mon C language source which can be implemented either on the FPGA or on the CPU. This allows the FPGA to act as a high-performance library call for common software functions such as matrix inversion and deep neural networks. 


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  • FPGA Virtex-4 LX Family 24192 Cells 90nm Technology 1.2V 363-Pin FCBGA
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