TABLE OF CONTENTS

• Preface
• WHY USE FPGAS?
  • APPLICATIONS
  • SOME TECHNOLOGY BACKGROUND
  • INSTANT SUMMARY
• FPGA Architectures
  • MORE ON PROGRAMMING TECHNOLOGIES
  • FINE-, MEDIUM-, AND COARSE-GRAINED ARCHITECTURES
  • LOGIC BLOCKS
  • LUT versus Distributed RAM versus SR
  • CLBS VERSUS LABS VERSUS SLICES
  • Slicing and Dicing
  • EMBEDDED RAMS
  • EMBEDDED MULTIPLIERS, ADDERS, ETC.
  • EMBEDDED PROCESSOR CORES
  • CLOCK MANAGERS
  • GENERAL-PURPOSE I/O
  • GIGABIT TRANSCEIVERS
  • INTELLECTUAL PROPERTY (IP)
  • SYSTEM GATES VERSUS REAL GATES
  • INSTANT SUMMARY
• Programming (Configuring) an FPGA
  • CONFIGURATION CELLS
  • ANTIFUSE-BASED FPGAS
  • SRAM-BASED FPGAS
  • USING THE CONFIGURATION PORT
  • USING THE JTAG PORT
  • USING AN EMBEDDED PROCESSOR
  • INSTANT SUMMARY
• FPGA vs. ASIC Designs
  • When You Switch from ASIC to FPGA Design, or Vice Versa
  • CODING STYLES
  • PIPELINING AND LEVELS OF LOGIC
  • ASYNCHRONOUS DESIGN PRACTICES
  • CLOCK CONSIDERATIONS
  • REGISTER AND LATCH CONSIDERATIONS
  • RESOURCE SHARING (TIME-DIVISION MULTIPLEXING)
  • STATE MACHINE ENCODING
  • TEST METHODOLOGIES
  • MIGRATING ASIC DESIGNS TO FPGAS AND VICE VERSA
  • INSTANT SUMMARY
• “Traditional” Design Flows
  • SCHEMATIC-BASED DESIGN FLOWS
  • HDL-BASED DESIGN FLOWS
  • INSTANT SUMMARY
• Other Design Flows
  • C/C ++ -BASED DESIGN FLOWS
  • DSP-BASED DESIGN FLOWS
  • EMBEDDED PROCESSOR-BASED DESIGN FLOWS
  • INSTANT SUMMARY
• Simulation Tools
  • SYNTHESIS (LOGIC/HDL VERSUS PHYSICALLY AWARE)
  • TIMING ANALYSIS
  • VERIFICATION IN GENERAL
  • FORMAL VERIFICATION
  • MISCELLANEOUS
  • INSTANT SUMMARY
• Choosing the Right Device
  • CHOOSING
  • TECHNOLOGY
  • BASIC RESOURCES AND PACKAGING
  • GENERAL-PURPOSE I/O INTERFACES
  • EMBEDDED MULTIPLIERS, RAMS, ETC.
  • EMBEDDED PROCESSOR CORES
  • GIGABIT I/O CAPABILITIES
  • SPEED GRADES
  • FUTURE FPGA DEVELOPMENTS
  • INSTANT SUMMARY