Hard Processors

Soft processors are a very suitable alternative for the development of FPSoCs, but when the highest possible performance is required, hard processors may be the only viable solution. Hard processors are commercial, usually propri- etary, processors that are integrated with the FPGA fabric in the same chip, so they can be somehow considered as another type of specialized hard- ware blocks. The main difference with the stand-alone versions of the same processors is that hard ones are adapted to the architectures of the FPGA devices they are embedded in so that they can be connected to the FPGA fabric with minimum delay. However, very interestingly, from the point of view of software developers, there is no difference, for example, in terms of architecture or ISA. 

There are obviously many advantages derived from the use of optimized, state-of-the-art processors. Their performance is similar to the correspond- ing ASIC implementations (and well known from these implementations); they have a wide variety of peripherals and memory management resources, are highly reliable, and have been carefully designed to provide a good performance/ functionality/power consumption trade-off. Documentation is usually extensive and detailed, and they have whole development and sup- port ecosystems provided by the vendors. There are also usually many ref- erence designs available that designers can use as starting point to develop their own applications. 

Hard processors have also some drawbacks. First, they are not scalable, because their fixed hardware structure cannot be modified. Second, since they are fine-tuned for each specific FPGA family, design portability may be limited. Finally, same as for stand-alone processors, obsolescence affects hard processors. This is a market segment where new devices with ever-enhanced features are continuously being released, and as a consequence, production of (and support for) relatively recent devices may be discontinued. 

The first commercial FPSoCs including hard processors were proposed by Atmel and Triscend.* For instance, Atmel developed the AT94K Field Programmable System Level Integrated Circuit series (Atmel 2002), which combined a proprietary 8-bit RISC AVR processor (1 MIPS/MHz, up to 25 MHz) with reconfigurable logic based on its AT40K FPGA family. Triscend, on its side, commercialized the E5 series (Triscend 2000), including an 8032 microcontroller (8051/52 compatible, 10 MIPS at 40 MHz). In both cases, the reconfigurable part consisted of resources accounting for roughly 40,000 equivalent logic gates, and the peripherals of the microcontrollers consisted of just a small set of timers/counters, serial communication interfaces (SPI, UART), capture and compare units (capable of generating PWM signals), and interrupt controllers (capable of handling both internal and external inter- rupt sources). None of these devices is currently available in the market, although Atmel still produces AT40K FPGAs. 

After only a few months, 32-bit processors entered the FPSoC market with the release of Altera’s Excalibur family (Altera 2002), followed by QuickLogic’s QuickMIPS ESP (QuickLogic 2001), Triscend’s A7 (Triscend 2001), and Xilinx’s Virtex-II Pro (Xilinx 2011b), Virtex-4 FX (Xilinx 2008), and Virtex-5 FXT (Xilinx 2010b). This was a big jump ahead in terms of processor architectures, available peripherals, and operating frequencies/ performance. 

Altera and Triscend already opted at this point to include ARM proces- sors in their FPSoCs, whereas QuickLogic devices combined a MIPS32 4Kc processor from MIPS Technologies † with approximately 550,000 equivalent logic gates of Via-Link fabric (QuickLogic’s antifuse proprietary technology). 

* Microchip Technology acquired Atmel in 2016, and Xilinx acquired Triscend in 2004.

† Imagination Technologies acquired MIPS Technologies in 2013.

FIGURE 3.12 SmartFusion architecture.

Xilinx Virtex-II Pro and Virtex-4 FX devices included up to two IBM PowerPC 405 cores and Virtex-5 FX up to two IBM PowerPC 440 cores. Only these three latter families are still in the market, although Xilinx recommends not to use them for new designs. 

It took more than 5 years for a new FPSoC family (Microsemi’s SmartFusion, Figure 3.12) to be released, but since then there has been a tremendous evolution, with one common factor: All FPGA vendors opted for ARM architectures as the main processors for their FPSoC platforms. Microsemi’s SmartFusion and SmartFusion 2 (Microsemi 2013, 2016) fami- lies include an ARM Cortex-M3 32-bit RISC processor (Harvard architecture, up to 166 MHz, 1.25 DMIPS/MHz), with two 32 kB SRAM memory blocks, 512 kB of 64-bit nonvolatile memory, and 8 kB instruction cache. It provides different interfaces (all based on ARM’s proprietary AMBA bus, described in Section 3.5.1) for communication with specialized hardware blocks or custom user logic in the FPGA fabric, as well as many peripherals to sup- port different communication standards (USB controller; SPI, I 2 C, and CAN blocks, multi-mode UARTs, or Triple-Speed Ethernet media access control). In addition, it includes an embedded trace macrocell block intended to ease system debug and setup. 

Altera and Xilinx include ARM Cortex-A9 cores in some of their most recent FPGA families, such as Altera’s Arria 10 (Figure 3.13), Arria V, and 

FIGURE 3.13 Arria 10 hard processor system.

Cyclone V (Altera 2016a,b) and Xilinx’s Zynq-7000 AP SoC (Xilinx 2014). The ARM Cortex-A9 is a 32-bit dual-core processor (2.5 DMIPS/MHz, up to 1.5 GHz). Dual-core architectures are particularly suitable for real-time operation, because one of the cores may run the OS and main application programs, whereas the other core is in charge of time-critical (real-time) functions. In both Altera and Xilinx devices, the processors and the FPGA fabric are supplied from separate power sources. If only the processor is to be used, it is possible to turn off power supply for the fabric, hence allowing power consumption to be reduced. In addition, the logic can be fully or par- tially configured from the processor at any time.* 

The main features of the ARM Cortex-A9 dual-core processor are as follows: 

• Ability to operate in single-processor, SMP dual-processor, or AMP dual-processor modes. 

• Up to 256 kB of on-chip RAM and 64 kB of on-chip ROM. 

• Each core has its own level 1 (L1) separate instruction and data caches, 32 kB each, and share 512 kB of level 2 (L2) cache. 

• Dynamic length pipeline (8–11 stages). 

• Eight-channel DMA controller supporting different data transfer types: memory to memory, memory to peripheral, peripheral to memory, and scatter–gather. 

• MMU. 

• Single- and double-precision FPU. 

• NEON media processing engine, which enhances FPU features by providing a quad-MAC and additional 64-bit and 128-bit register sets supporting single-instruction, multiple-data (SIMD) and vector floating-point instructions. NEON technology can accelerate multimedia and signal processing algorithms such as video encode/ decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. 

• Available peripherals include interrupt controller, timers, GPIO, or 10/100/1000 tri-mode Ethernet Media Access Control, as well as USB 2.0, CAN, SPI, UART, and I 2 C interfaces. 

• Hard memory interfaces for DDR4, DDR3, DDR3L, DDR2, LPDDR2, flash (QSPI, NOR, and NAND), and SD/SDIO/MMC memories. 

• Connections with the FPGA fabric (distributed logic and specialized hardware blocks) through AXI interfaces (described in Section 3.5.1.3). 

• ARM CoreSight Program Trace Macrocell, which allows the instruction flow being executed to be accessed for debugging pur- poses (Sharma 2014). 

At the time of writing of this book, the two most recently released FPSoC platforms are Altera’s Stratix 10 (Altera 2015d) and Xilinx’s Zynq UltraScale+ (Xilinx 2016b), both including an ARM Cortex-A53 quad-core processor. Most of the features of the ARM Cortex-A53 processor (Figure 3.14) are already present in the ARM Cortex-A9, but the former is smaller and has less power consumption. The cores in Stratix 10 and Zynq UltraScale+ families can operate up to 1.5 GHz, providing 2.3 DMIPS/MHz performance. 

In addition, Zynq UltraScale+ devices include an ARM Cortex-R5 dual- core processor and an ARM Mali-400 MP2 GPU, as shown in Figure 3.14b, resulting in a heterogeneous multiprocessor SoC (MPSoC) hardware archi- tecture. The ARM Cortex-R5 is a 32-bit dual-core real-time processor,* capable of operating at up to 600 MHz and providing 1.67 DMIPS/MHz perfor- mance. Cores can work in split (independent) or lock-step (parallel) modes. 

FIGURE 3.14 Processing systems of (a) Altera’s Stratix 10 FPGAs and (b) Xilinx’s Zynq UltraScale+ MPSoCs.

Lock-step operation is intended for safety-critical applications requiring redundant systems. 

The main features of each core are as follows: 

• 32 kB L1 instruction and data caches and 128 kB TCM for highly deterministic or low-latency applications (real-time single-cycle access). All memories have ECC and/or parity protection. 

• Interrupt controller. 

• MPU. 

• Single- and double-precision FPU. 

• Embedded trace macrocell for connection to ARM CoreSight debug- ging system. 

• AXI interfaces (described in Section 3.5.1.3). 

The ARM Mali-400 GPU is a low-power graphics acceleration processor, capable of operating at up to 667 MHz. Its 2D vector graphics are based on OpenVG 1.1,* whereas 3D graphics are based on OpenGL ES 2.0. † It supports Full Scene Anti-Aliasing and Ericsson Texture Compression to reduce exter- nal memory bandwidth and is fully autonomous to operate in parallel with the ARM Cortes-A53 application processor. It consists of five main blocks: 

1. Geometry processor, in charge of the vertex processing stage of the graphics pipeline: It generates lists of primitives and accelerates building of data structures for pixel processors. 

2. Pixel processors (two), which handle the rasterization and fragment pro- cessing stages of the graphics pipeline: They produce the framebuffer results that screens display as final images. 

3. MMU: Both the geometry processor and the pixel processors use MMUs for access checking and translation. 

4. L2 cache: Geometry and pixels processors share a 64 kB L2 read-only cache. 

5. Power management unit, supporting power gating for all the other blocks. 

Some devices in the Zynq UltraScale+ family also include a video codec unit in the form of specialized hardware block (i.e., as part of the FPGA resources), supporting simultaneous encoding/decoding of video and audio streams. Its combination with the Mali-400 GPU results in a very suitable platform for multimedia applications. 

* OpenVG 1.0 is a royalty-free, cross-platform API for hardware accelerated two-dimensional vector and raster graphics. 

† OpenGL ES is a royalty-free, cross-platform API for full-function 2D and 3D graphics on embedded systems. 

All building blocks the processing system of Zynq UltraScale+ devices consists of are interconnected among themselves and with the FPGA fabric through AMBA AXI4 interfaces (described in Section 3.5.1.3). 

Once hard and soft processors have been analyzed, it is important to emphasize that their features and performance (although extremely impor- tant*) are not the only ones to consider when addressing the design of FPSoCs. The resources available in the FPGA fabric (analyzed in Chapter 2) also play a fundamental role in this context. 

Given the increasing complexity of FPSoC platforms, the availability of efficient software tools for design and verification tasks is also of paramount importance in the potential success of these platforms in the market. To real- ize how true this is, one has to just think about what it may take to debug a heterogeneous multicore FPSoC, where general-purpose and real-time OSs may have to interact (maybe also with some proprietary kernels) and share a whole bunch of hardware resources (memory and peripherals integrated in the processing system, implemented in the FPGA fabric, available there as specialized hardware blocks, or even implemented in external devices). Tools and methodologies for FPGA-based design are analyzed in Chapter 6, where special attention is paid to SoPC design tools (Section 6.3).