ZedBoard Audio in Vivado IP Integrator

In this exercise we will be focusing on adding an audio controller IP instance to an existing Vivado IP Integrator design, and the modifications which must be made to the Zynq Processor block in order to use the ADAU1761 audio codec on the ZedBoard. Such modifications include the addition of a second PL fabric clock and the enabling of the I2C interface for the communication of control signals between the Zynq PS and the codec.

We will begin by adding an instance of the audio controller IP to the block design.

(a) In the Vivado IP Integrator block design canvas, right-click and select Add IP. Search for audio and double-click on zed_audio_ctrl, to add an instance to the block design.

The zed_audio_ctrl block should now be visible on the canvas, as shown in Figure 5.7.

(b) Make the initial connection between the Zynq PS and the zed_audio_ctrl block by clicking Run Connection Automation.

You should notice that there are still four unconnected ports. These are required to be made external to connect to the physical pins of the ZedBoard’s audio codec.

(c) Hover the mouse pointer over each of the unconnected interfaces on the zed_audio_ctrl block until the cursor changes to a pencil. Right-click and select Make External. Alternatively, select the interface and use the keyboard shortcut Ctrl+T.

The next step is to make the necessary modifications to the Zynq7 PS block.

(d) Double-click on the Zynq7 Processing System block to open the Re-customize IP window, as shown in Figure 5.8.

This view allows you to make changes to the configuration of the Zynq PS. As IP Integrator is board aware, all of the basic settings that apply to the ZedBoard have been made for us. There are a few changes, however, that must be made when using the audio codec.

First we will add a second PL fabric clock as a separate 10 MHz clock is required for the MCLK pin on the audio codec.

(e) Click on Clock Configuration in the Page Navigator panel on the left hand side of the window. Expand PL Fabric clocks in the Clock Configuration panel, and enable FCLK_CLK1. Change the Requested Frequency of FCLK_CLK1 to 10 MHz, as shown in Figure 5.9.

Next, we must enable one of the Zynq PS’s I2C communication interfaces to allow the PS to communicate with the audio codec.

(f) Select MIO Configuration from the Page Navigator panel.

This configuration view allows us to enable/disable the PS peripherals. These peripherals can be routed through the dedicated Multiplexed I/Os (MIO) on the device, or through the Extended Multiplexed I/Os (EMIOs) which route to the PL fabric.

As we want to communicate with the audio codec (which is connected to fabric pins of the Zynq device) we will be routing the I2C signals through the EMIOs.

(g) Enable the I2C 1 peripheral in the MIO Configuration panel. EMIO should automatically be selected for IO, as shown in Figure 5.10.

No more changes to the Zynq PS are required.

(h) Close the Re-customize IP window and apply the changes to the PS by clicking OK.

The IP Integrator canvas should update, and the Zynq7 Processing System block should now look like Figure 5.10.

You should note the addition of the two new interfaces, IIC_1 and FCLK_CLK1. As these will be driving signals on the audio codec, which is situated on the board (external to the Zynq device), we must make these external.

(i) Hover the mouse pointer over each of the IIC_1 and FCLK_CLK1 interfaces on the processing_system1_0 block until the cursor changes to a pencil. Right-click and select Make External. Alternatively, select the interface and use the keyboard shortcut Ctrl+T.

The final addition to the Block design that we need to make, is to add two GPIO instances:

• Single-channel GPIO with a width of 2-bits to connect to the audio codec’s ADDR pins. 

• Dual-channel GPIO with a width of 32-bits to connect to the push buttons and slide switches on the ZedBoard, for user input.

First we will add the GPIO to connect to the codec’s ADDR pins.

(j) In the Vivado IP Integrator block design canvas, right-click and select Add IP. Search for gpio and double-click on AXI_GPIO, to add an instance to the block design.

(k) Run Connection Automation for the axi_gpio_0/S_AXI interface, to connect the GPIO controller to the Zynq PS via the AXI Interconnect.

(l) Open the Re-customize IP window by double-clicking on the axi_gpio_0 block. The window, as shown in Figure 5.12, will open.

(m) Select the IP Configuration tab.

Enter 2 as the GPIO Width, as shown in Figure 5.13, and close the window by clicking OK.

(n) Make the GPIO interface of the axi_gpio_0 block external.

Next we will add a second instance of the AXI GPIO Controller.

(o) Add an instance of the AXI_GPIO IP to the block design and Run Connection Automation for the axi_gpio_1/S_AXI interface, to connect the GPIO controller to the Zynq PS via the AXI Interconnect. 

(p) Double-click on the axi_gpio_1 block to open the Re-customize IP window.  In the IP Configuration tab, select the option to Enable Dual Channel, and click OK.

You should see that the axi_gpio_1 block now has two output ports, 1 each to connect to the push buttons and the slide switches on the ZedBoard:

(q) Run Connection Automation for /axi_gpio_1/GPIO and select BTNs_5Bits as the option for Select Board Interface.  Click OK. 

(r) Run Connection Automation for /axi_gpio_2/GPIO1 and select SWs_8Bits as the option for Select Board Interface.  Click OK. 

(s) Select the Address Editor tab from the Block Design window, as highlighted in Figure 5.14.

(t) Click the Expand All button, as highlighted in Figure 5.14. Check the assigned Offset Address and Range for each of the peripheral Cells.

If they do not match those in Figure 5.14, you must reassign the addresses by following the procedure in this step. If they match those in Figure 5.14, you can skip this step and move on to Step (u).

• Highlight all of the peripheral Cells by holding the Ctrl key on the keyboard while clicking on each cell in turn. 

• Right-click on any of the selected Cells and select Unmap Segment. This will unmap the addresses for all of the peripherals 

• Expand the Unmapped Slaves section and highlight all of the Cells. 

• Right-click on any of the Cells and select Assign Address. 

• The Offset Address and Range for each peripheral Cell should now match those in Figure 5.14. If they don’t, you can edit the Offset Address and Range values manually.

(u) Return to the block design by selecting the Diagram tab in the IP Integrator window. 

(v) Click the Regenerate Layout button, , to regenerate the layout of the various IP blocks and make the block design easier to follow. Your complete block design should be similar to Figure 5.15.

(w) Save the block design.

Before we can run synthesis and implementation for our design, we must generate the RTL files for our block design.

(x) Generate a top-level HDL wrapper file, by right-clicking on ip_design in the Sources tab and selecting Create HDL Wrapper. In the Create HDL Wrapper window, select Let Vivado manage wrapper and auto-update, and click OK.

The next task that we have to do in Vivado before we can synthesis and implementation of the design, is to add a constraints file which will map the external interfaces of our design to specific pins on the Zynq device.

(y) Select Add Sources form the Project Manager section of Flow Navigator. In the Add Sources window, select Add or Create Constraints, and click Next. In the Add or Create Constraints window, select Add Files. Navigate to C:/Zynq_Book/sources/adventures_with_ip_integrator/constraints, select adventures_with_ip.xdc, and click OK.

Click Finish to close the Add Sources window, and import the constraints file.

(z) Open the constraints file by expanding the Constraints section of Sources tab, and double clicking on adventures_with_ip.xdc.

The top section of the file contains the constraints which map the individual bits of the LEDs_out interface to the corresponding pins on the Zynq device, and you will have seen these before in the first exercise of the previous tutorial.

The bottom section of the file, as shown in Figure 5.16, contains the constraints which map the various external ports of the design which relate to the audio codec, to their corresponding pins on the Zynq device.

Next, we will create a bitstream so that we can program the PL of the Zynq device with our design.

(aa) In Flow Navigator, select Generate Bitstream from the Program and Debug section. At the No Implementation Results Available window, click Yes to launch synthesis and implementation.

When bitstream generation is complete, select Open Implemented Design in the Bitstream Generation Completed window, and click OK.

Finally, we can export the hardware to the SDK, where we will create a software application to control the system in the next exercise.

(ab)Select File > Export > Export Hardware for SDK from the Menu Bar. Ensure that the options to Include Bitstream and Launch SDK are selected, and click OK.

This concludes this exercise on audio of the ZedBoard. You should now be familiar with:

• Making the required changes to the Zynq PS in order to use the audio codec on the ZedBoard. 

• Making the required external connections to allow the Zynq PL to be connected to the audio codec via the external Zynq device pins. 

• Using a constraints file to map the external interfaces of the design which relate to the audio codec, to the corresponding pins on the Zynq device.