This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Technical Tutorials > The Zynq Book Tutorials > Adventures with IP Integrator > Importing IP to the Vivado IP Catalog

Importing IP to the Vivado IP Catalog

FONT SIZE : AAA

In this exercise we will be concentrating on importing existing custom IP into the Vivado IP Catalog. We will be importing the various IP blocks which we created in The Zynq Book Tutorial IP Creation.

We will start by creating a new Vivado Project.

(a) Launch Vivado 2014.1 and create a new project called adventures_with_ip in the C:\Zynq_Book directory, ensuring that the option to Create project subdirectory is selected. Select VHDL as the Target language and the ZedBoard as the Default Part. 

(b) From Flow Navigator, select IP Catalog from the Project Manager section.

The IP Catalog will open in the Workspace, as seen in Figure 5.1.

Vivado IP Catalog.png

In order to import our custom IP into the IP Catalog, we must add a new software repository to the IP Catalog. We will create a new directory to act as our IP repository and all of our IP sources to it.

(c) In Windows Explorer, navigate to the location: C:\Zynq_Book\ip_repo. This is the IP repository that we created in Tutorial 4.

We must now add each of the IP sources which we created in The Zynq Book Tutorial IP Creation to our repository.

As the LED controller IP is already present in the IP repository, we do not need to import it.

(d) In Windows Explorer, navigate to

C:\Zynq_Book\hdl_coder_lms\hdl_prj\ipcore\lms_pcore_v1_00_a and copy the archived IP ZIP file, xilinx.com_user_lms_pcore_1.0.zip to the ip_repo directory.

(e) In Windows Explorer, navigate to C:\Zynq_Book\hls_nco\solution1\impl\ip and copy the archived IP ZIP file, xilinx_com_hls_nco_1_0.zip to the ip_repo directory.

That completes the copying of our custom made IP sources to our newly created IP repository. We will now add one more IP source to our repository — an existing IP block which controls the audio codec on the ZedBoard.

(f) In Windows Explorer, navigate to

C:\Zynq_Book\sources\adventures_with_ip_integrator\ip and copy the archived IP ZIP file, zed_audio_ctrl.zip to the ip_repo directory that we located in Step (c).

If you have not completed the previous tutorial, a master set of the IP sources is contained in C:\Zynq_Book\sources\adventures_with_ip_integrator\ip which you can copy into the repository for use in this tutorial.

Now that we have created the IP repository and added all of our existing IP sources, we can now add the repository to the IP Catalog.

(g) In the Vivado IP Catalog tab, click the IP Settings button, , as highlighted in Figure 5.1.

The IP Settings window will open, as shown in Figure 5.2.

IP Settings Window.png

(h) Click Add Repository in the IP Repositories panel, and browse to

C:\Zynq_Book\ip_repo.

Click Select to add the repository to the IP Catalog.

You should see that the LED Controller IP is already present in the IP in Selected Repository pane as it is in un-archived format.

We must now add the other IP sources to the repository by un-archiving them.

(i) In the IP in Selected Repository panel, shown in Figure 5.2, click Add IP.

The Select IP TO Add To Repository window will open:

Select IP to Add to Repository.png

Select xilinx.com_user_led_controller_1.0.zip and click OK. This will extract the archived IP sources into a usable format in the repository.

(j) Repeat this procedure for the remaining IP sources:

• xilinx.com_user_lms_pcore_1.0.zip 

• xilinx_com_hls_nco_1_0.zip 

• zed_audio_ctrl.zip

The resulting IP in Selected Repository panel is shown in Figure 5.4.

All IP sources added to IP Catalog.png


Click OK.

With all of our IP now imported into the IP Catalog, we can now create an IP Integrator block design which incorporates all of the IP blocks.

(k) In Flow Navigator, select Create Block Design

(l) In the Create Block Design window, set the Design name as ip_design, and click OK.

(m) In the block design canvas, right-click and select Add IP

In the Search box, enter led_controller and double-click led_controller_v1_0 to add an 

instance of the LED controller IP to the design.

(n) Repeat Step (m) searching for:

nco and double-clicking Nco 

lms and double-clicking lms_pcore_v1_0

We have now added all of the custom IP that we created in the previous tutorial. At this point we will avoid adding the audio controller IP, as it is the focus of the next exercise.

In order to connect and control all of the IP, we must now add an instance of a Zynq Processor.

(o) In the block design canvas, right-click and select Add IP. In the Search box, enter zynq and double-click ZYNQ7 Processing System.

At this stage, Designer Assistance should be available:

image.png

(p) Click Run Block Automation for processing_system7_0 and click OK to complete configuration. 

(q) Run Connection Automation for each of the three IP blocks, to connect them to the Zynq7 Processing System block, via and AXI Interconnect block.

You may recall that to allow the LED Controller block to control the LEDs on the board, the LEDs_out port must be made external.

(r) Hover the mouse pointer over the LEDs_out interface on the led_controller block until the cursor changes to a pencil. Right-click and select Make External. Alternatively, select the interface and use the keyboard shortcut Ctrl+T.

Notice that the lms_pcore_0 block has two unconnected input ports, as highlighted in Figure 5.5.

LMS IP block.png

These are the CLK and reset ports of the IP, and must be connected in order for the IP to be functional.

(s) Hover the mouse pointer over the IPCORE_CLK interface on the lms_pcore_0 block until the cursor changes to a pencil. Click and drag the mouse pointer until it is hovering over the wire that connects to the AXI_Lite_ACLK interface and the wire is highlighted, as shown in Figure 5.6, and release the mouse button to create the connection.

Manually connecting the LMS IP CLK.png

You should also see a pop-up message notifying you of the net which you are connecting to.

(t) Repeat the procedure of the previous step to, this time, connect the IPCORE_RESETN interface to the wire which connects to the AXI_Lite_ARESETN interface.

At this stage we must now add and configure the audio controller IP, and so we will conclude this first exercise on importing custom IP to the Vivado IP Catalog. You should now be familiar with:

• Adding an IP repository to the Vivado IP Catalog. 

• Importing and adding archived IP files to a custom IP repository. 

• Adding custom IP to a Vivado IP Integrator block design.

Note: Do not close the current Vivado project as we will be using it again in the next exercise.

  • XC3S400AN-5FGG400C

    Manufacturer:Xilinx

  • FPGA Spartan-3AN Family 400K Gates 8064 Cells 770MHz 90nm Technology 1.2V Automotive Medical 400-Pin FBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

    RoHS:

  • XC4025E-3HQ304C

    Manufacturer:Xilinx

  • FPGA XC4000E Family 25K Gates 2432 Cells 0.35um Technology 5V 304-Pin HSPQFP EP
  • Product Categories: FPGAs

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC5206-5VQ100I

    Manufacturer:Xilinx

  • FPGA XC5200 Family 10K Gates 784 Cells 83MHz 0.5um Technology 5V 100-Pin VTQFP
  • Product Categories:

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC2C256-7PQG208I

    Manufacturer:Xilinx

  • CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V 208-Pin PQFP
  • Product Categories: CPLDs

    Lifecycle:Active Active

    RoHS:

  • XC3S400-FG456EGQ

    Manufacturer:Xilinx

  • Xilinx BGA Voltage regulator tube
  • Product Categories: Voltage regulator tube

    Lifecycle:Any -

    RoHS:

Need Help?

Support

If you have any questions about the product and related issues, Please contact us.