TIMING ANALYSIS

Static Timing Analysis   

The most common form of timing verification in use today is classed as STA.  Conceptually, this is quite simple, although in practice things are, as usual,  more complex than they might at first appear.   

The timing analyzer essentially sums all of the gate and track delays forming each path to give you the total input-to-output delays for each path. (In  the case of pipelined designs, the analyzer calculates delays from one bank of  registers to the next.)   

Prior to place-and-route, the analyzer may make estimations as to track  delays. Following place-and-route, the analyzer will employ extracted parasitic  values (for resistance and capacitance) associated with the physical tracks to  provide more accurate results. The analyzer will report any paths that fail to meet their original timing constraints, and it will also warn of potential timing  problems (e.g., setup and hold violations) associated with signals being presented to the inputs of any registers or latches.

—Technology Trade-offs—  

● STA is particularly well suited to classical synchronous designs and pipelined architectures. The main advantages of STA are that it is relatively  fast, it doesn’t require a test bench, and it exhaustively tests every possible  path into the ground. On the downside , static timing analyzers are little  rascals when it comes to detecting false paths that will never be exercised  during the course of the design’s normal operation. Also, these tools aren’t  at their best with designs employing latches, asynchronous circuits, and  combinational feedback loops.

Statistical Static Timing Analysis   

STA is a mainstay of modern ASIC and FPGA design flows, but it’s starting to  run into problems with the latest process technology nodes. At the time of writing,  an increasing number of folks are starting to design at the 45-nano node, with the  32-nano node expected to see mainstream adoption starting around 2011/2012.   As previously discussed, in the case of modern silicon chips, interconnect  delays dominate logic delays, especially with respect to FPGA architectures.  In turn, interconnect delays are dependent on parasitic capacitance, resistance,  and inductance values, which are themselves functions of the topology and  cross-sectional shape of the wires.   

The problem is that, in the case of the latest technology process nodes,  photo lithographic processes are no longer capable of producing exact shapes.  Thus, as opposed to working with squares and rectangles, we are now working  with circles and ellipsoids. Feature sizes like the widths of tracks are now so  small that small variations in the etching process cause deviations that, although  slight, are significant with relation to the main feature size. (These irregularities are made more significant by the fact that in the case of high-frequency  designs, the so-called skin-effect comes into play, which refers to the fact that  high-f requency signals travel only through the outer surface, or skin, of the  conductor.) Furthermore, there are variations in the vertical plane of the track’s  cross section caused by processes like chemical mechanical polishing (CMP).   

As an overall result, it’s becoming increasingly difficult to calculate track  delays accurately. Of course, it is possible to use the traditional engineering  fallback of guard-banding (using worst-case estimations), but excessively conservative design practices result in device performance significantly below the  silicon’s full potential, which is an extremely unattractive option in today’s  highly competitive marketplace. In fact, the effects of geometry variations are  causing the probability distributions of delays to become so wide that worstcase numbers may actually be slower than in an earlier process technology!

One potential solution is the concept of the statistical static timing analyzer (SSTA). This is based on generating a probability function for the delay associated with each signal for each segment of a track, then evaluating the total  delay probability functions of signals as they propagate through entire paths.  The problem is that SSTA is very complex and the distribution functions are—  in reality—not nice Gaussian curves. Just to add to the fun and frivolity, some  of the distribution functions tend to be time-based; as a piece of equipment at  the foundry undergoes “ wear ” over time, for example, this can affect some of  the probability distributions. Having said this, by 2008 most of the “ big boys ”  supplying tools to design and verify integrated circuits (e.g., Cadence, Magma,  Synopsys, etc.) had an SSTA offering of one form or another (some are better  than others). Many of the folks designing chips at the 45-nano node are using  SSTA, and many observers believe that the use of SSTA will be mandatory at  the forthcoming 32-nano node (actually, in addition to timing analysis, statistical techniques are starting to appear in other analysis engines, such as power  consumption and noise/signal integrity).