SYNTHESIS (LOGIC/HDL VERSUS PHYSICALLY AWARE)

Logic/HDL Synthesis Technology   

Traditional logic synthesis tools appeared on the scene around the early to  mid-1980s. Depending on whom you are talking to, these tools are now often  referred to as HDL synthesis technology.   

The role of the original logic/HDL synthesis tools was to take an RTL representation of an ASIC design along with a set of timing constraints and to  generate a corresponding gate-level netlist. During this process, the synthesis  application performed a variety of minimizations and optimizations (including  optimizing for area and timing).   

Around the middle of the 1990s, synthesis tools were augmented to understand the concept of FPGA architectures. These architecturally aware applications could output a LUT/CLB-level netlist, which would subsequently be  passed to the FPGA vendor’s place-and-route software ( Figure 7-9 ).   

—Technology Trade-offs—  

● In real terms, the FPGA designs generated by architecturally aware synthesis tools were 15 to 20 percent faster than their counterparts created using  traditional gate-level synthesis offerings.

Physically Aware Synthesis Technology   

The problem with traditional logic/HDL synthesis is that it was developed  when logic gates accounted for most of the delays in a timing path, while track  delays were relatively insignificant. This meant that the synthesis tools could  use simple wire-load models to evaluate the effects of the track delays. (These  models were along the lines of: One load gate on a wire equates to x pF of  capacitance; two load gates on a wire equates to y pF of capacitance; etc.) The  synthesis tool would then estimate the delay associated with each track as a  function of its load and the strength of the gate driving the wire.   

This technique was adequate for the designs of the time, which were implemented in multimicron technologies and which contained relatively few logic  gates by today’s standards. By comparison, modern designs can contain tens of  millions of logic gates, and their deep submicron feature sizes mean that track  delays can account for up to 80 percent of a delay path. When using traditional  logic/HDL synthesis technology on this class of design, the timing estimations  made by the synthesis tool bear so little resemblance to reality that achieving  timing closure can be well-nigh impossible.   

For this reason, ASIC flows started to see the use of physically aware synthesis somewhere around 1996, and FPGA flows began to adopt similar techniques circa 2000 or 2001.

FAQ  

What does “ physically aware ” really mean?  

Of course there is a variety of different definitions as to exactly what the term  physically aware synthesis implies. The core concept is to use physical information earlier in the synthesis process, but what does this actually mean? For example, some companies have added interactive floor-planning capabilities to the  front of their synthesis engines, and they class this as being physical synthesis or  physically aware synthesis. For most folks, however, physically aware synthesis  means taking actual placement information associated with the various logical  elements in the design, using this information to estimate accurate track delays,  and using these delays to fine-tune the placement and perform other optimizations. Interestingly enough, physically aware synthesis commences with a firstpass  run using a relatively traditional logic/HDL synthesis engine ( Figure 7-10 ).

Retiming, Replication, and Resynthesis   

In this section, we’ll discuss several concepts related to physical synthesis that  were defined earlier: retiming , replication , and resynthesis .   

As an example, let’s assume a pipelined design whose clock frequency is  such that the maximum register-to-register delay is 15 ps. Now let’s assume  that we have a situation as shown in Figure 7-11a , whereby the longest timing path in the first block of combinational logic is 10 ps (which means it has  a positive slack of 5 ps), while the longest path in the next block of combinational logic is 20 ps (which means it has a negative slack of 5 ps).   

Once the initial path timing, including routing delays, has been calculated,  combinational logic is moved across register boundaries (or vice versa, depending on your point of view) to steal from paths with positive slack and donate to  paths with negative slack ( Figure 7-11b ). Retiming is very common in physically aware FPGA design flows because registers are plentiful in FPGA devices.   

Replication is similar to retiming, but it focuses on breaking up long interconnect. For example, let’s assume that we have a register with 4 ps of positive  slack on its input. Now let’s assume that this register is driving three paths,  whose loads each see negative slack ( Figure 7-12a ).   

By replicating the register and placing the copies close to each load, we can  redistribute the slack to make all of the timing paths work ( Figure 7-12b ). 

Last, but not least, the concept of resynthesis is based on the fact that there  are many different ways of implementing (and placing) different functions.  Resynthesis uses the physical placement information to perform local optimizations on critical paths by means of operations like logic restructuring, reclustering, substitution, and possible elimination of gates and wires.

Insider Info  

In the real world, the capabilities of the various synthesis engines, along with  associated features like autointeractive floor planning, change on an almost daily  basis, and the various vendors are constantly leapfrogging each other. There’s also  the fact that different engines may work better (or worse) with different FPGA  vendors ’ architectures. One thing to look for is the ability (or lack thereof) of the  engine to infer things automatically, like clocking elements and embedded functions, from your source code or constraints files without your having to define  them explicitly.