Processors on FPGAs

There are two categories of processor solutions possible on Xilinx FPGAs:

• Soft processors

• Hard processors

You can choose either of these depending on the amount of control processing and I/O required for your application. The cost of the overall solution will also play a role in making the decision.

Soft Processors

Soft processors make use of the FPGA fabric for implementing the processors. For low speed (200 MHz and below), soft processors are a good option. These come in multiple fl avors and are user confi gurable. Depending on the nature of the applica- tion, you can choose to trim down the functionality from the processors.

At the lowest end, you can implement an 8-bit processor with bare minimal instruc- tion set. One example of such a processor is PicoBlaze ™ from Xilinx. This processor is a good replacement for state machines. PicoBlaze does not have a compiler tool chain and hence requires the program to be written in assembly language. This program is stored in the local memory available on the FPGA as a memory store. The simplicity of the architecture enables a processor which can be implemented in just about 26 slices.

As a step up, Xilinx introduced a 32-bit highly confi gurable processor named MicroBlaze ™ in early 2000. This RISC-based soft processor is capable of achiev- ing clock speed of around 400 MHz on the UltraScale FPGA architectures. It sup- ports an option of a three-stage or a fi ve-stage pipeline, confi gurable cache, optional multiply and divide units, optional barrel shifter, single- and double-precision fl oating- point unit, and more. Every additional feature selected in hardware will lead to usage of FPGA resources and can have impact on the max frequency ( F max ) possible. The choice can be made based on the needs of the user application. For example, if there are many multiply operations to be done, it is better to enable a hard multiplier. It can save over 1000 clock cycles for every multiply operation done over a software library-based solution (Fig. 6.1 ).

MicroBlaze processor.png

Fig. 6.1 MicroBlaze processor

In addition to the soft processors from Xilinx, you can also build your own processors or procure one from IP vendors and open source. There have been implementations of ARM done on Xilinx FPGAs in academia as well as industry. There have also been implementations of processors with reduced instruction set targeted toward specifi c applications. MicroBlaze has been optimized for FPGA implementation and is usually better suited for both resource count as well as F max .

Hard Processors

While soft processor can cater to the needs of mid-level applications, there are a few factors that make hardened processors on FPGAs a key requirement. Some applica- tions require high-speed processing of 1 GHz and above. There are several software applications which are targeted toward standard processors like ARM. Retargeting these to other processors specifi c to FPGAs could take up a lot of effort and reveri- fi cation (Fig. 6.2 ).

Xilinx introduced Zynq-7000 ™ family of devices which includes a complete SoC with two Cortex-A9™ processors along with a confi gurable mix of peripher- als. These include high-speed peripherals such as GigE and USB and low-speed peripherals like SPI , I2C , CAN , and UART . The processing system (PS) also includes controllers for various volatile memories ( DDR3 , DDR2 , DDR3L ) as well as fl ash memories ( QSPI, NOR and NAND ). By hardening the most commonly used blocks in the SoC, Xilinx has enabled saving FPGA logic for the key acceleration logic rather than using it for interfacing to components on the board.

Zynq-7000 block diagram (not to scale).png

Fig. 6.2 Zynq-7000 block diagram (not to scale)

The PS is built such that the SoC can be used even without the programmable logic ( PL ) fabric turned on. This enables the software users to be productive even without the FPGA design has been created. Section 6.5 (Putting It All Together) talks about some of the ways to use Zynq-like devices.

The architecture was further extended in the Zynq UltraScale+ MPSoC ™ shown in Fig. 6.3 . Xilinx raised the compute power of the SoC by introducing four Cortex A-53™ cores and two Cortex-R5™ cores. In addition to these proces- sors, there is a GPU as part of the SoC as well. With MPSoC, Xilinx has also introduced a host of high-speed peripherals which include SATA , DisplayPort , PCIe , and USB 3.0 . These are built on top of high-speed SerDes which are part of the SoC. Xilinx extended the memory support to DDR4 as well. Security and isolated power domains have been two major advancements in Zynq UltraScale+ MPSoC. The processor and other masters in the SoC can have secure access to specifi c peripheral/memory through the Xilinx Peripheral Protection Units (XPPUs) and Xilinx Memory Protection Units (XMPUs). Since the SoC packs a lot of powerful peripherals, the power consumption has to be controlled. Xilinx has split the SoC in a lower power domain and full power domain making it easier for customers to split their application appropriately and shut down peripherals when not in use.

Zynq UltraScale MPSoC.png

Fig. 6.3 Zynq UltraScale+ MPSoC

TABLE OF CONTENTS

Soft Processors

Hard Processors