Creating IP in Vivado HLS

In this final exercise, we will creating an IP core that will implement the functionality of an NCO. The tool that we will be using is Vivado HLS, and we shall explore some of the features which allow us to specify arbitrary precision fixed-point data types, as well as the directives required to export IP with an AXI-Lite slave interface, to allow the IP core to interface with the Zynq processor.

We will start by creating a new project in Vivado HLS.

(a) Launch Vivado HLS by double-clicking on the Vivado HLS desktop icon: , or by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1 > Vivado HLS > Vivado HLS 2014.1 

(b) When Vivado HLS loads, you will be presented with the Getting Started screen, as in Figure 4.24.

(c) Select the option to Create New Project and the New Vivado HLS Project Wizard will open, as in Figure 4.25.

Enter hls_nco as the Project name, and C:\Zynq_Book as Location. Ensure that the options match those in Figure 4.25, and click Next.

(d) The Add/Remove Files dialogue will appear. This is where existing C-based source files can be added to the project, or new files created.

Enter nco as the Top Function and click Add Files. 

Navigate to C:\Zynq_Book\sources\hls_nco and select nco.cpp. Click Open. 

The dialogue should now resemble Figure 4.26.

(e) A second Add/Remove Files dialogue will appear. This is where C-based testbench files can be added to the project, or new files created.  

Click Add Files. and navigate to C:\Zynq_Book\sources\hls_nco. Select nco_tb.cpp and click Open to add the testbench file to the project. 

Click Next. 

(f) The Solution Configuration dialogue will open. Here we will be selecting the part which we will be targeting. In this particular case we will be targeting the Zynq-7020 on the ZedBoard, but if you have a different development board, it is easy to choose your particular board instead.

Click the selection button, , in the Part Selection pane.

The Device Selection Dialog will open.

As we are targeting the ZedBoard, select Boards in the Specify pane and choose ZedBoard

Zynq Evaluation and Development Kit, as in Figure 4.27.

Click OK to close the dialogue and return to the New Project Wizard.

(g) Click Finish to close the New Project Wizard and to create the project.

The Vivado HLS workspace will open.

(h) In the Explorer panel, expand the Source and Test Bench headings. You should see the source files that we specified in the New Project Wizard, as in Figure 4.28. 

(i) Open nco.cpp and examine the contents of the file.

You should notice the inclusion of the header file ap_fixed.h on the first line. This is the arbitrary precision fixed-point library which adds support for the use of fixed-point data types in C++.

The next thing that you should see is the global declaration of a = 4096 value array:

const ap_fixed<16,2> sine_lut[4096] .

This forms the sinewave lookup table. It is defined as an array of type ap_fixed<16,2>, which means that all values are16-bit, signed fixed-point (2 integer bits and 14 fractions bits). Further information on fixed-point data types in Vivado HLS can be found in Chapter15 - Vivado HLS: A Closer Look of the Zynq Book.

The functionality of the NCO is contained in the function:

void nco (ap_fixed<16,2> *sine_sample, ap_ufixed<16,12> step_size)

It takes two arguments:

• *sine_sample — A pointer to a 16-bit, signed fixed-point variable which forms the output sample of the NCO. 

• step_size — 16-bit, unsigned fixed-point value which provides the step size input for the NCO.

(j) Explore the nco function, ensuring that you understand it all. Open nco_tb.cpp. This is the testbench file which is used to ensure that the functionality of the C-based source file is correct.

Explore the code in the file, ensuring that you understand the functionality.

This is a simple file which opens a text file in write-mode, to allow you to output the sinusoidal samples. It then calls the nco function from within a for-loop in order to generate a finite

number of sinusoidal samples, which are then output to the text file. The text file is formatted in a way which easily allows you to import the samples into MatLab for analysis.

Note: The location of the output file is determined by the following line in the testbench file:

char *outfile = "E:\\nco_sine.m";

You should change the output file path accordingly to a location on your local machine.

We will now run a C simulation.

(k) Click the Run C Simulation button, , from the Main Toolbar. The C Simulation Dialog window will open. Click OK to run the simulation with the default settings.

The C simulation will run, and you should see the following output in the Console window:

The sine wave samples that were generated by the NCO will have been output to the location which you specified in the previous step.

If you wish, you can import the sine wave samples into MATLAB using the output file to verify that the NCO has correctly generated a sine wave. This should be done at your own discretion, and will not be covered in this exercise.

The process of HLS has been covered previously in The Zynq Book Tutorial: Designing With Vivado High Level Synthesis, and you should refer to it for more detailed information on the various steps involved. For the purposes of this exercise, it is presumed that you have a reasonable knowledge of the Vivado HLS tool.

As we want to allow our NCO peripheral to be controlled by a Zynq PS, it is necessary to give it an AXI interface. This is done in Vivado HLS through the use of directives.

(l) Ensure that nco.cpp is the active source file, and select the Directive tab in the right-hand side of the Vivado HLS workspace, as shown in Figure 4.29.

First, we will define the interface of the NCO as an AXI-Lite slave.

(m) Right-click on nco in the Directive tab, and select Insert Directive.

As the Directive Type, select RESOURCE.

and select AXI4LiteS [adapter] as the core, from the pop-up list.

Leave Destination as Directive File, and click OK.

We will now define the NCO as having a ap_ctrl_none interface, to remove unneeded control signals.

(n) Right-click on nco in the Directive tab, and select Insert Directive.

As the Directive Type, select INTERFACE.

and select ap_ctrl_none as the mode, from the drop-down list. 

Leave Destination as Directive File, and click OK.

Finally, we will be defining the two variables, sine_sample and step_size, as ports on the AXI-LIte slave interface.

(o) Right-click on sine_sample in the Directive tab, and select Insert Directive. As the Directive Type, select RESOURCE. and select AXI4LiteS [adapter] as the core, from the pop-up list. Leave Destination as Directive File, and click OK. 

(p) Repeat the previous step for the step_size variable in the Directive tab.

On completion, the Directive tab should look like Figure 4.30.

We can now run HLS.

(q) Run C Synthesis by clicking the Run C Synthesis button, , from the Main Toolbar. 

(r) Click the Export RTL button, , from the Main Toolbar.

The Export RTL Dialog window will open, as shown in Figure 4.31.

(s) Select IP Catalog as the Format Selection.  

If you choose, you can edit the IP Identification data by clicking the Configuration button. 

(t) Click OK to generate the IP core.

When RTL Generation has completed, a directory named impl will be visible in the Explorer panel

This directory contains the ip subdirectory which contains the generated IP package.

Take a moment to explore the contents of the ip directory.

With the IP generated, the next step would be to include it in an IP Integrator design (which will be covered in the next tutorial). For future reference, however, it is worth briefly describing how this would be done. 

In order to include HLS generated IP in IP Integrator, it must first be added to the Vivado IP Catalog. To do this you must add the output from HLS to an IP repository. This can be achieved by either adding the HLS generated output directory to an existing IUP repository directory, or by creating a new repository. In either case, the directory is the same. In this case:

C:\Zynq_Book\hls_nco\solution1\impl\ip

We have now completed the generation of the NCO component as an IP Integrator compatible AXI-Lite block. You should now be familiar with:

• Specifying directives in Vivado HLS designs which define the control interface of the exported RTL. 

• The process of specifying and AXI4 interface for a design, to enable a Vivado HLS system to be easily connected to the Zynq PS. 

• Exporting a Vivado HLS design as an IP core that is compatible with the Vivado IP Catalog and IP Integrator.