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QDRIV SRAM (quad data rate IV synchronous random access memory) introduced in 2014 is the latest offering from Cypress Semiconductor on the synchronous SRAM category. QDRIV has lower latency and does not have any timing parameters
that affect effi ciency. The Vivado tool provides various options for you to customize the memory controller similar to DDR4 .
QDRIV memory device has two independent bidirectional data ports. Both the ports operate at DDR data rate and can be used for both read and write transactions. One common DDR address bus is used to access both the ports; rising edge is used for accessing one port and the falling edge for the other port. The ports are named port A and port B . Each port has its independent read and write clocks. Port A address will be sampled at the rising edge of the address clock, and the port B address will be sampled on the falling edge of the address clock.
There are two types of QDRIV parts: XP and HP. HP parts do not have any restriction on the access between two ports. XP parts have some restrictions and the bank access rules are listed below:
• Port A can have any address on rising edge of the address clock. There is no restriction for port A .
• Port B can access any other bank address on the falling edge of the clock other than the bank address used by port A on the rising edge.
• Port B can access any address in the falling edge if there was address presented on rising edge for port A .
• From the rising edge of the input clock cycle to the next rising edge of the input clock, there is no address restriction.
The most important aspect for you would be the throughput of the memory con- troller and the storage requirements. A 36 bit QDRIV memory operating at 1066 MHz will have a theoretical peak bandwidth of 153.3 GB/s. The bandwidth of the mem- ory subsystem would depend largely on the memory confi guration and the access pattern. The confi guration is fi xed during the initial selection. The access pattern varies based on the traffi c in the system. QDRIV interface does not have any timing parameter that affects the performance. It has only one restriction on bank access between the two ports. If the memory is accessed in a way that takes advantage of the QDRIV features, then 100 % bandwidth can be achieved which is not possible in other memory technologies.
Effi ciency equation mentioned in Eq. 5.1 (Sect. 5.5.1 ) is applicable to QDRIV as well. The access pattern of the user will have an effect on performance for XP QDRIV devices. In a given clock cycle, port B cannot access the same bank address as the bank address used by port A . If the traffi c pattern is such that there is banking violation in port B , then the memory controller would have to pause the traffi c to take care of the banking restriction. Other than that the only time there will be an effect on effi ciency would be the read to write and write to read turnaround times. The user would have to make sure to group the reads and writes to get maximum effi ciency. Since port A and port B have independent data buses, there is no
Fig. 5.12 Port A and Port B access with confl ict
restriction on read and write between the ports. The turnaround wait time is within the port data bus.
Figure 5.12 shows an example of confl ict when port B accesses the same bank address as port A . On every memory controller clock cycle, the commands for port A and port B can be accepted. The corresponding port commands will be sent on the rising and falling edge of the memory clock to the QDRIV SRAM device by the memory controller. Usually the memory controller will be operated at a lower clock frequency than the memory interface frequency for timing reasons. In this example it is shown that the memory controller operates at the memory interface frequency. The controller would have to stall certain number of clock cycles to resolve the confl ict. In QDRIV case the stalling would be only one clock cycle unless other factors come into play.
QDRIV memory is attractive for applications that would require high effi ciency for random traffi c. Latency would also be critical for those applications and QDRIV provides low latency at higher data rates. Typical applications that would use QDRIV are high-speed networking, communication, and any application that would have access that would be random in nature.
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