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RLDRAM3 (reduced latency dynamic random access memory), introduced in 2012, is the latest offering from Micron Technology, Inc., on the reduced latency DRAM category. RLDRAM3 has the advantage of reduced latency combined with good storage capacity. Similar to DDR4 the Vivado tool provides various options for you to confi gure the memory controller.
Effi ciency equation mentioned in Eq. ( 5.1 ) (Sect. 5.5.1 ) is applicable to RLDRAM3 as well. The memory timing parameters and the memory controller architecture have a big effect on the performance of the memory subsystem. RLDRAM3 has two important timing parameters that affect performance: tRC and tWTR. tRC ( row cycle time) is defi ned as “after a read, write, or auto refresh command is issued to a bank , a subsequent read, write, or auto refresh cannot be issued to the same bank until tRC has passed.” tWTR (write to read to same address) is defi ned as “write command issued to an address in a bank ; a subsequent read command to the same address in the bank cannot be issued until tWTR has passed.”
RLDRAM3 has 16 banks . As shown in Fig. 5.10 , if the access is scheduled in such a way that the same bank to bank access comes in after tRC time requirement,
Fig. 5.10 Access across banks
Fig. 5.11 Bank access with tRC and tWTR
then the effi ciency will be high. There will not be any idle cycles between the read and write commands. If the traffi c pattern is such that the tRC time is not satisfi ed, then the controller has to pause so that tRC time can be elapsed before issuing the command. The read to write and write to read turnaround as per specifi cation is one memory clock cycle. Whenever there is a turnaround requirement, the controller has to pause for one memory clock cycle. Some memory controllers due to clock ratios and I/O requirements might end up waiting for more than one clock cycle.
Write followed by read to the same address in the bank will have a larger wait time. The tWTR parameter comes into effect when a write is followed by read to the same address in the bank . The controller would have to pause the traffi c and wait for tWTR to elapse in this scenario which will have an effect on effi ciency. As shown in Fig. 5.11 , the write to read to the same address in the bank has to be spaced apart to satisfy the tWTR requirements. Figure 5.11 also shows an example of write to read to different addresses within a bank . In this scenario only the turnaround time and the tRC requirement will come into effect. The same is true for read to write within a bank for any address; the turnaround time and the tRC requirement will come into effect.
The low-latency and high-bandwidth characteristics of RLDRAM-3 are highly suited for high-bandwidth networking, L3 cache, high-end commercial graphics, and other applications that require the RLDRAM3 features.
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