Creating IP in MathWorks HDL Coder

In this exercise, we will be creating an IP core which will perform the function of an LMS noise cancellation filter. Mathworks HDL Coder will be used to transform an existing Simulink blockbased model into an RTL description which will be packaged for use in the Vivado IP Catalog. The.

We will start by opening the Simulink model in MatLab.

Before starting this exercise, you are required to copy some source files into a new working directory.

(a) In Windows Explorer, navigate to C:\Zynq_Book\sources\hdl_coder_lms and copy the contents of the directory to a new directory called C:\Zynq_Book\hdl_coder_lms.

(b) Launch MatLab by navigating to Start > All Programs > MATLAB > R2013a > MATLAB R2013a

Note: This workbook uses version R2013a of MatLab. If you have a different MatLab version you will need to replace R2013a with your own version (i.e. R2012a/R2012b).

MatLab will open and you will see the main workspace, as shown in Figure 4.18(or a variation thereof).

(c) Enter C:\Zynq_Book\hdl_coder_lms as the working directory, as highlighted in Figure 4.19.

In the Current Folder pane, you should also see four files:

• original_speech.wav — A short audio clip of speech. 

• setup.m — Performs setup commands to import the audio samples into the MatLab workspace and set the system sample rate accordingly. 

• lms.slx — A simulink model which implements and LMS noise cancellation process. 

• playback.m —Can be used to verify the LMS filtering process via audio playback of the various stages.

The setup commands in setup.m are automatically called when the Simulink simulation is initialised.

(d) Open the LMS Simulink model by double-clicking on lms.slx in Current Folder pane. The model should open and you should see the LMS system, as shown in Figure 4.20.

The model features two sources:

• a Sine Wave block which generates tonal noise. 

•A From Workspace block which imports the audio samples from the MatLabe Workspace.

The tonal noise is then added to the audio samples to create a corrupted audio signal.

In order to generate HDL code for the Simulink LMS model using HDL Coder, the inputs to the system must be in fixed-point numerical format. Two Data Type Conversion blocks are used to convert the corrupt audio signal and the tonal noise signal to fixed-point format. The fixed-point signals are then input to an LMS subsystem, which we will explore in the next step.

At the output of the LMS subsystem, the error signal, e(k), is input to a scope along with the corrupt audio and tonal noise inputs, for visual inspection of the signals. Two To Workspace blocks are also present to allow the LMS output and the corrupt audio signals to be output to the MatLab workspace for audio playback.

(e) Drill down into the LMS subsystem block by double-clicking on it. You will see the system in Figure 4.21.

It features a single LMS Filter block. As we are not interested in the Output signal, it is unconnected.

(f) Open the LMS Filter Block Parameters by double-clicking on the LMS Filter block. 

Take a moment to explore the parameters. You should be able to determine that there are 16 adaptive filter coefficients and a step size of 0.1.

(g) Close the Parameters window, and return to the main Simulink model by clicking the Up To Parent button, .

We will be generating HDL code for the LMS subsystem only.

Right-click on the LMS subsystem and select HDL Code > HDL Workflow Advisor. 

The HDL Workflow Advisor window will open, as in Figure 4.22.

The HDL Workflow Advisor guides you through the steps required to generate RTL code for your design.

(h) In the left-hand panel, expand Set Target and select 1.1. Set Target Device and Synthesis Tool.

Here we specify the output format of the RTL and the target platform.

(i) In the Input Parameters pane, select IP Core Generation as the Target workflow, and Generic Xilinx Platform as the Target platform, as shown in Figure 4.23.

(j) Click Run This Task to apply the settings. 

(k) Select Set Target Interface from the left hand panel.  Here we specify the target interface for the HDL code generation. In the Input Parameters pane, select Coprocessing - blocking as the Processor/FPGA synchronization. This will automatically infer an AXI4-Lite interface for all ports in the design, and specify a memory address for each. 

(l) Click Run This Task to apply the settings. 

(m) Expand Prepare Model for HDL Code Generation in the left hand panel, and select Check Global Settings.

Here, model-level settings will be checked to verify if the model is ready for HDL code generation.

(n) Click Run This Task to check the model-level settings.

If this step fails, click Modify All to allow HDL Workflow Advisor to modify the settings. This step should now pass, and you will be presented with a table of the results.

The next few steps are all checks, and can be performed in batch.

(o) Right-click on Check Sample Times in the left hand pane, and select Run to Selected Task. This will perform the checks one after another to prevent you from running each individually.  All check should pass.

The final steps involve specifying basic settings about the RTL code, such as what language to use (VHDL/Verilog), and what code generation reports to generate. Finally the HDL code will be generated.

(p) Expand HDL Code Generation in the left hand pane, and further expand Set Code Generation Options.

Click on Set Basic Options.

(q) Select VHDL as the Language in the Target pane.  You can also select any of the Code generation reports that you would like. 

(r) Select Set Advanced Options in the left hand panel. Here you can specify more advanced options for the HDL code. We will be leaving the values as default, but you may wish to explore the settings for future use.

(s) Right-click on Set Advanced Options, and select Run to Selected Task to apply the settings. 

(t) Finally, select Generate RTL Code and IP Core from the left hand panel. This is the step which will finally generate the HDL code for out LMS IP Core. Set the IP core name as lms_pcore and click Run This Task.

Once HDL Coder has finished generating the HDL code, the Code Generation Report window will open. This provides a summary of the HDL Coder results and provides further information on the target interface and clocking.

The final stage of creating our LMS IP core is to package it with IP Packager so that we can use it in IP Integrator designs. To do this we will need to create a new Vivado project.

(u) Launch Vivado and create a new project called lms_packaging at the following location:

C:\Zynq_Book\hdl_coder_lms, ensuring that the option to create a project subdirectory is selected. Also select the VHDL as the target language, and the ZedBoard as the default part.

For more detail on the process of creating a new Vivado project, refer to Step (a) of Exercise 4A.

(v) When the project has been created and opened, select Tools > Create and Package IP from the menu bar, and Click Next. 

(w) Select the option to Package a specified directory, and click Next.

(x) Enter C:/Zynq_Book/hdl_coder_lms/hdl_prj/ipcore/lms_pcore_v1_00_a as the IP Location. 

(y) Click Next to move to the Edit in IP Packager Project Name dialogue, and click Next to accept the default Project Name and Project Location. 

(z) At the Summary window, and click Finish to launch IP Packager. 

(aa) In the left hand panel of the IP Packager window, select IP Ports and Interfaces.

The IP Interfaces panel will open, and you should see that IP Packager has identified the individual AXI ports, but has not inferred an AXI interface.

To infer an AXI interface:

(ab)Right-click on a blank section of the IP Ports and Interfaces pane, and select Auto Infer Interface .

(ac) The Auto Infer Interface Chooser window will open:

Select aximm from the list, as shown, and click OK.

The individual AXI ports in our design will be mapped to an AXILite interface.

(ad)Select IP Addressing and Memory from the left hand panel. Here, IP Packager has incorrectly specified an address Range of 4294967296. Click on the Range, and change the value to 32.

(ae) Finally, select Review and Package from the left hand menu.  Review the information provided, and click Package IP.

This completes the generation of an LMS component from Mathworks HDL Coder. You should now be familiar with:

• Using the Simulink block-based design environment for the design and simulation of IP. 

• Using the HDL Workflow Advisor to guide you through the steps of generating RTL code and IP cores for existing Simulink designs.

• Packaging HDL Coder generated IP blocks in IP Packager for use in Vivado IP Integrator designs.