DDR4 SDRAM

DDR4 SDRAM (double data rate synchronous dynamic random access memory) introduced in 2014 is the latest (at the time of writing this book) memory standard that is widely used in the industry.

The Vivado tool provides various options for you to customize the memory con- troller. Based on the system requirements, you can select the options given below:

• Memory device selection: density of the device, DQS to DQ ratio, column address strobe read and write latency, memory speed grade, component, DIMM, SODIMM, RDIMM, 3DS, or LRDIMM

• Memory controller options: user interface selection, effi ciency switches, address- ing options for various payloads, data width, and ODT options

• FPGA options: FPGA banks and pins to be used, FPGA termination options, VREF options, and clocking options (input clock to the memory controller IP)

The most important aspect for you would be the throughput of the memory con- troller and the storage requirements. A 64 bit DDR4 memory operating at 3200 MT/s will have a theoretical peak bandwidth of 25,600 MB/s. The bandwidth of the mem- ory subsystem would depend largely on the memory confi guration and the access pattern. The confi guration is fi xed during the initial selection. The access pattern varies based on the traffi c in the system. You can take advantage of the memory controller features which will help in improving the practical bandwidth.

Performance

Effi ciency of a memory controller is represented by Eq. ( 5.1 ):

Efficiency =Numberof clockcyclesDQbuswasbusy

/ Numberof memoryc lockcycles

The effi ciency percentage will determine the bandwidth of the system. A 64 bit memory operating at 3200 MT/s with 80 % effi ciency will have an effective band- width of 20,480 MB/s compared to theoretical bandwidth of 25,600 MB/s. The memory timing parameters and the memory controller architecture have a big effect on the performance of the memory subsystem. The memory timing parameters are requirements as per memory protocol, and commands can be scheduled in a way that the wait times for servicing timing parameters can be hidden or avoided.

To access a memory to perform a read or write operation, row access commands are required to open and close rows in the memory. If a row in the bank needs to be accessed, fi rst the row in the bank has to be opened. Opening of row ( activate com- mand) has wait times associated with it to move the data from the DRAM cell arrays to the sense amplifi ers and having it ready for read or write operations. To close a row in a bank , a precharge command has to be issued. The precharge command has

Fig. 5.6 Bank grouping

for four bank group

confi guration

Bank grouping.png

its own timing requirements to reset the sense amplifi ers and get it ready for another row access command. At a given time only, one row can be kept open in a bank of memory. DDR4 memory has 16 banks and at any given time one row in each of the 16 banks can be kept open.

To get the required performance, the number of row access commands has to be minimized, and more of column access commands (read or write) have to be issued. DDR4 memories also have a concept called bank groups . Each bank group will have four banks associated with it as shown in Fig. 5.6 .

The new feature in DDR4 is that access across bank groups has less access time compared to access within the bank group . In terms of bank access, the example shown in Fig. 5.7 has less access time which helps in performance. The example shows write commands; the same is true for read commands as well. The memory controller will be able to keep multiple banks open and can hide the row access times between the column commands. The burst length for DDR4 is eight, and due to the dual data rate for every four memory clock cycles, there will be eight data transfers. Back to back column commands can be issued only every four memory clock cycles. Between the column commands, the row commands can be interleaved to open and close banks. Column access that changes bank groups every four clock cycles will have the advantage of minimum access time. Access across the bank groups in most of the scenarios will avoid idle cycles between the column accesses.

The other access pattern that can hide the row access penalties to a certain extent is shown in Fig. 5.8 . The performance of this access pattern will not be as good as the performance of access pattern shown in Fig. 5.7 . By switching to different banks within the bank groups or across the bank groups gives the fl exibility for controller to have multiple banks open and schedule commands in such a way that the row access times can be hidden. Switching of banks within the bank groups is not guar-

Access across bank groups.png

Fig. 5.7 Access across bank groups

Access to different banks within a bank group.png

Fig. 5.8 Access to different banks within a bank group

Access to different rows within a bank.png

Fig. 5.9 Access to different rows within a bank

anteed to avoid the idle cycles between column accesses as the access times are higher in this scenario compared to accesses across bank groups .

In terms of performance, random access pattern will incur more row access pen- alties. An example of a pattern that will have low performance is shown in Fig. 5.9 . In the example shown in Fig. 5.9 , the read commands go to different row addresses in bank 0 that is present in bank group 2. The accesses are within the bank , and every time a different row is opened, the existing row in the bank has to be closed and the new one opened. The controller has to wait for the closing and opening times before issuing the column commands. The timing requirements for the acti- vate and precharge commands will be more than the time that is between the two column commands. This results in idle cycles between column accesses.

The data bus for DDR4 is a bidirectional bus. Every time there is a change from write to read or read to write, it takes time to reverse the direction of the data bus. Most controllers have reordering functionality built in them to group reads and writes to minimize the occurrence of turnaround time.

The memory controller solutions from Xilinx provide options for you to map the user address to the address bus of the SDRAM . Depending upon the option selected by you, the user interface in the controller maps the address from the user to the SDRAM address bus. Based on your selection, the parts of the address bits would be assigned to rank , bank group , column , and row bits of the SDRAM . The mapping can have an impact on the memory controller performance. The controller would be able to make use of the controller resources and able to keep the data bus busy with column commands.

There are also memory maintenance commands like refresh and ZQCS that have to be issued to the SDRAM periodically. The memory controller by default will issue the maintenance commands periodically to satisfy the SDRAM requirements. When the memory controller issues these maintenance commands, a long burst might be broken up affecting the effi ciency. The maintenance commands also have the requirement to close all the open banks , and they have to be opened again after the completion of the maintenance commands. The user can choose to take control of the maintenance commands and issue it through the user interface signals to improve effi ciency. Care should be taken to make sure the SDRAM timing requirements are met when the user takes over the responsibility to issue the maintenance commands.

DDR4 has wide use in many applications . DDR4 comes in various form factors to suit the different system requirements. The common use of the memory is in desktop, laptop, and servers as the main system memory. DDR4 is highly suited for processor-based systems and in any application that require mass storage. LPDDR4 memory interface has similar features like DDR4 with additional low- power fea- tures. LPPDR4 memory is not discussed separately and majority of the concepts described in DDR4 are applicable to it.

TABLE OF CONTENTS

Performance