Creating IP in HDL

With Zynq devices comprising of both PS and PL parts, most IP that is created to run in PL should be able to communicate with software running on the PS. This requires that IP should be packaged with an interface that is compatible with the PS (in this case the AXI interface).

When creating IP in HDL, Vivado provides a set of AXI interface templates which can be created and customised via the Create and Package IP Wizard. The wizard, as the name suggests, facilitates two major functions: the creation of AXI4 IP peripherals; and the packaging of existing source files into an IP package which is compatible with the IP Integrator tool.

In this exercise we will actually be making use of both of these features to firstly create an AXI4- Lite IP template to which we will add functionality to allow the LEDs on the ZedBoard to be controlled via a software application running on the Zynq PS. Once the functionality has been added to the template, the source files will be packaged into an IP Integrator compatible IP block which will be included in a simple Zynq processor system.

We will start by creating a new Vivado project.

(a) Launch Vivado by double-clicking on the Vivado desktop icon: , or by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1 > Vivado 2014.1 

(b) Select Create New Project from the Getting Started screen. 

(c) The New Project dialogue will open. Click Next. 

(d) At the Project Name dialogue, enter led_controller as the Project name and C:/Zynq_Book as Project location.

Make sure that you select the option to Create project subdirectory. Ensure that all options match Figure 4.1.

Click Next.

(e) Select RTL Project at the Project Type dialogue, and ensure that the option Do not specify sources at this time is not selected:

Click Next.

(f) Select VHDL as the Target language in the Add Sources dialogue.  If existing sources, in the form of HDL or netlist files, were to be added to the project they could be imported at this stage.  As we do not have any sources to add to the project, click Next. 

(g) The Add Existing IP (optional) dialogue will open. If existing IP sources were to be included in the project, they could be added here. As we do not have any existing IP to add, click Next. 

(h) The Add Constraints (optional) dialogue will open. This is the stage were any physical or timing constraints files could be added to the project.  As we do not have any constraints files to add, click Next. 

(i) The Default Part dialog will open. Here we will be selecting the Zynq part which we are targeting. In this particular case we will be targeting the Zynq-7020 on the ZedBoard, but if you have a different development board, it is easy to choose your particular board instead. Select Boards from the Specify pane, ZedBoard Zynq Evaluation and Development Kit as the Display Name, and finally select the Board Rev which you have. In Figure 4.2 version C of the ZedBoard has been selected.

Click Next.

(j) Review the New Project Summary dialogue, and click Finish to create the project.

With the new project created, we can begin the process of creating our HDL-based IP.

(k) From the menu bar, select Tools > Create and Package IP ., as in Figure 4.3, to launch the Create and Package IP Wizard.

(l) The Create and Package IP Wizard dialogue will launch, as shown in Figure 4.4.

Click Next.

The Choose Create Peripheral or Package IP dialogue (Figure 4.5) is where we specify whether to create a new peripheral template file or to package existing source files into an IP core.  In our case we want to create a new IP template.

(m) Select Create new AXI peripheral, as shown in Figure 4.5.

Click Next.

The Peripheral Details dialogue allows you to specify the Vendor, Library, Name and Version (VLNV) information, as well as other details, for the new peripheral, leaving the IP Location as the default.

(n) Fill in the details as shown in Figure 4.6.

Click Next.

The Add Interface dialogue allows you to specify the AXI4 interface(s) that will be present in your custom peripheral. Here you can specify:

• Number of interfaces 

• Interface type (AXI-Lite, AXI-Stream or AXI-Full) 

• Interface mode (slave or master) 

• Interface data width

Features specific to individual interface types will also be available when the corresponding type is selected.

As our peripheral is a simple controller for the LEDs which only requires single values to be transferred to it, an AXI-Lite slave interface is sufficient. Only one memory mapped register is required for our simple controller, but as the minimum number that can be specified in the dialogue is 4, we will choose that.

(o) Specify the Add Interface dialogue as shown in Figure 4.7.

Click Next.

(p) Review the information in the Create Peripheral dialogue, which details the output files which will be created.

Select the option to Edit IP. This will create the IP peripheral files and create a new Vivado project where the functionality of the peripheral can be modified in the source HDL code, and then packaged.

Click Finish to close the Wizard and create the peripheral template.

A new Vivado project, named edit_led_controller_v1_0, will open.

In the Sources pane, you should see two HDL source files:

As we specified our target language as VHDL in Step (f) earlier, the template files have been generated in VHDL. Had we specified Verilog as the target language, Verilog source files would have been created.

The two source files are:

• led_controller_v1_0.vhd — This file instantiates all AXI-Lite interfaces. In this case, only one interface is present. 

• led_controller_v1_0_S00_AXI.vhd — This file contains the AXI4-Lite interface functionality which handles the interactions between the peripheral in the PL and the software running on the PS.

The IP Packager pane will also be open in the Workspace:

The information that we specified about our peripheral in Step (n) will be visible.

We can now add the functionality to our led_controller peripheral. We will be adding a new output port to the peripheral template to allow it to connect to the LED pins on the Zynq device, as well as assigning the value received from the Zynq PS to the new output port.

(q) Open led_controller_v1_0_S00_AXI.vhd by double-clicking on it in the Sources pane. The file will open in the Workspace.  

(r) Scroll down until you see the following comment in the entity port declaration:

(s) Scroll to the bottom of the file. You should see the following comment:

This assigns the value that is received from the Zynq PS (stored in the signal slv_reg0) to the output port that we created in the previous step.

(t) Save the file by selecting File > Save File from the Menu Bar, or using the keyboard shortcut Ctrl+S.

(u) Open led_controller_v1_0.vhd by double-clicking on it in the Sources pane. The file will open in the Workspace.

We must once again create a new output port to the top-level source file, and map it to the equivalent port that we created in the AXI4-Lite interface file in the previous steps.

(v) Scroll down until you see the following comment in the entity port declaration:

As we added a new port to the AXI4-Lite interface file, we must also add it to the component declaration in the top-level file.

(w) Scroll down until you see the comment:

Finally, we must add a port mapping between the LED output ports of the top-level file and the AXI4-Lite interface file.

(x) Scroll down until you see the comment:

(y) Save the file.

Now that we have made the necessary modifications to the peripheral source files, we must repackage the IP to merge the changes.

(z) Return to IP Packager by selecting the Package IP - led_controller tab in the Workspace:

IP Packager will detect the changes to the source files, and the areas which need refreshed will be highlighted with the following icon: . You should see that the following two areas need refreshed:

(aa) Select IP Customization Parameters in the IP Packager pane.

You should see the following information message at the top of the pane:

Click Merge changes from IP Customization Parameters Wizard

This will update the IP Packager information to reflect the changes made in the HDL source files.

NOTE: This process updates IP Packager information for all areas. You should see that the area of IP Ports no longer needs updated, and the icon has now been removed.

To verify that IP Packager has updated the IP Ports area, we will open it and check.

(ab)Select IP Ports and Interfaces from the IP Packager pane.

You should notice that the LEDs_out port that we added to the source files has been added to the IP Ports and Interfaces pane:

The final step in creating our new IP peripheral, is to package the IP.

(ac) Select Review and Package from the IP Packager pane. 

(ad)In the After Packaging panel, click edit packaging settings at the bottom:

(ae) In the Automatic Behaviour panel, enable the option to Create archive of IP:

This makes a ZIP file archive of the packaged IP.

(af) Click OK to apply the setting. 

(ag)Review the information provided in the Review and Package window, and click Re-Package IP. 

(ah)The changes made to the IP peripheral will be included in the repackaged IP, and the Vivado project will close.

We will now return to our original Vivado project, and create a simple Zynq processor block design to check that the functionality of our LED controller peripheral.

To start, we will create a new Block Design and add the IP peripheral which we just created to the design.

(ai) In the Flow Navigator window, select Create Block Design from the IP Integrator section. Enter led_test_system in the Design name box, and click OK to create the blank design.

(aj) Right-click anywhere in the blank canvas, and select Add IP. Alternatively, use the keyboard shortcut Ctrl+I. This will bring up to pop-up IP Catalog window. Enter led in the Search box, and double-click led_controller_v1_0 to add an instance of the LED controller IP to the design.

An led_controller_v1_0 block will now be present in the block design, as shown in Figure 4.8.

The 8-bit LEDs_out port that we added to the peripheral is present on the right side of the block.

To enable the peripheral to connect to the LEDs on the ZedBoard, we must make the LEDs_out port external. This allows the output port to be connected to specific physical pins on the Zynq device, which are connected to the LEDs.

(ak) Hover the mouse pointer over the LEDs_out interface (the little black stub next to the interface name) on the led_controller block until the cursor changes to a pencil. Right-click and select Make External. Alternatively, select the interface and use the keyboard shortcut Ctrl+T.

The block design should now resemble Figure 4.9.

The next step is to add a Zynq Processing System block to the design and connect the LED Controller to it.

(al) Add an instance of the Zynq7 Processing System, using the same procedure as in Step (aj).

(am)The Designer Assistance message at the top of the canvas will appear:

Click Run Block Automation and select processing_system7_0.

An information message will appear. Ensure that Apply Board Preset is selected, and click OK. This will make all necessary modifications to the Zynq processing system that relate to the board preset (in this case the ZedBoard) and make required external connections.

The next step that has to be carried out to the block design, is to connect the LED Controller to the Zynq Processing System. This step can also be carried out using Designer Assistance.

(an)In the Designer Assistance message, click Run Connection Automation and select led_controller_0/S00_AXI.

An information message will appear. Click OK.

This will add some additional blocks to the design which are required to connect the LED Controller to the Zynq Processing System.

Our block design is now complete.

(ao)Validate the design by selecting Tools > Validate Design from the Menu Bar. Alternatively, select the Validate Design button, , from the Main Toolbar, or use the keyboard shortcut F6.

Dismiss the Validate Design message by clicking OK.

We can now generate the HDL files for the design.

(ap)In the Sources pane, right-click on the led_test_system block design and select Create HDL Wrapper.

Select Let Vivado manage wrapper and auto-update and click OK. 

This will create the top-level HDL file for the design.

We must now connect the LEDs_out port of the design to the correct pins on the Zynq device. This is done through the specification of constraints in an XDC file.

(aq)In the Flow Navigator window, select Add Sources from the Project Manager section.

The Add Sources dialogue will open.

Select Add or Create Constraints, and click Next.

(ar) Click Create File. The Create Constraints File dialogue will open. Select XDC as the File type and enter led_constraints as the File name. Click OK.

(as) Click Finish to create the file and close the dialogue. 

(at) In the Sources tab, expand the Constraints entry and open the newly created XDC file by double-clicking on led_constraints.xdc. The file will open in the Workspace.

(au)Add the following lines to the constraints file. Alternatively, they can be copied from the source file available at C:\Zynq_Book\sources\led_controller:

This connects each individual bit of the LEDs_out port to a specific pin on the Zynq device. The specific pins are connected to the LEDs on the board.

(av) Save the constraints file.

Our simple design is now complete. We can now generate a bitstream.

(aw)In Flow Navigator, select Generate Bitstream from the Program and Debug section.

If a dialogue window appears prompting you to save your design, click Save.

A dialogue window may open requesting that you launch synthesis and implementation before starting the Generate Bitstream process. If it does, click Yes to accept.  The combination of running the synthesis, implementation and bitstream generation processes back-to-back may take a few minutes, depending on the power of your computer system.

(ax) When bitstream generation is complete a dialogue window will open to inform you that the process as been completed. Select Open Implemented Design, and click OK.

With the bitstream generation complete, the final step in Vivado is to export the design to the SDK, where we will create the software application that will allow the Zynq PS to control the LEDs on the ZedBoard.

(ay) Select File > Export > Export Hardware for SDK. from the Menu Bar. The Export Hardware for SDK dialogue window will open. Ensure that the options to Include bitstream and Launch SDK are selected, and Click OK.

The SDK will launch.

(az) Once the SDK has launched, create a new Application Project by selecting File > New > Application Project from the Menu Bar.

In the New Project dialogue, enter LED_Controller_test as the Project name. 

By default the option to create a new board support package will be selected.  Click Next.

(ba)In the Templates dialogue, select Empty Application, and click Finish.

You should recall that when we created the peripheral in the previous stages of this exercise that a set of software driver files were generated. We must now point SDK to those driver files. This is done by adding a new repository to the SDK project.

(bb)Navigate to Xilinx Tools > Repositories in the Menu Bar.

In the Repositories Preferences window, click on New, as shown in Figure 4.10.

(bc)Browse to the directory C:\Zynq_Book\ip_repo\led_controller_1.0, as in Figure 4.11, and click OK.

(bd)Close the Repository Preferences window by clicking OK.

Upon closing the preferences window, SDK will automatically scan the repository and rebuild the project to include the driver files.

We must now assign the newly imported drivers to the LED Controller peripheral.

(be)The system.mss tab should be open in the Workspace. If it is not, open it by expanding LED_Controller_test_bsp in Project Explorer and double-clicking on system.mss. 

(bf) At the top left of the system.mss tab, click Modify this BSP’s Settings.

The Board Support Package Settings window will open, as in Figure 4.12.

(bg)Select drivers from the left-hand menu. From the list of components in the Drivers pane, identify led_controller_0 and select led_controller from the drop-down menu in the Driver column, as shown in Figure 4.13.

Click OK.

The project will now rebuild.

We can now create a simple C application to control the LEDs. In this instance we will be importing a pre-written source file.

(bh)In Project Explorer, right-click on LED_Controller_Test and select Import.

In the Import window, expand General and double-click on File System. Click Browse in the top right corner, and navigate to C:\Zynq_Book\sources\led_controller. Click OK.

In the right-hand panel, select led_controller_test_tut_4A.c and click Finish.

The project will once again rebuild to include the new source file.

Open led_controller_test_tut_4A.c and examine the functionality.

Before launching the application on the ZedBoard, we must program the Zynq PL and create a new terminal connection.

(bi) From the Menu Bar, select Xilinx Tools > Program FPGA.

The Bitstream entry should already be populated with the corresponding bitstream that we exported from Vivado earlier. 

Click Program, to program the Zynq PL.

NOTE: Once the device has successfully been programmed, the DONE LED on the ZedBoard will turn blue.

(bj) Select the Terminal tab from the Console window at the bottom of the workspace, as in Figure 4.14.

(bk)Click the Connect icon (as highlighted in Figure 4.14).

(bl) The Terminal Settings window will open. Configure the settings as specified in Figure 4.15.

NOTE: The value of the Port entry will vary depending on which the USB UART cable is connected to.  In order to determine this value on a Windows system, open the Device Manager and identify the COM port.

(bm)Click OK to initiate the new Terminal connection.

Now that the Zynq PL is programmed, and the Terminal connection has been created, we can program the Zynq PS with our software application.

(bn)In Project Explorer, right-click on LED_Controller_test and select Run As > Launch on Hardware (GDB), as shown in Figure 4.16.

(bo)Switch to the Terminal tab of the Console window, and confirm that the LED value is being output, as in Figure 4.17.

You should also see the LEDs on the ZedBoard displaying the corresponding LED values.

This concludes this exercise on designing Zynq IP in HDL. You should now be familiar with:

• Creating AXI interface templates with the Create and Package IP Wizard. 

• Adding functionality to HDL IP peripherals in Vivado and IP Packager. 

• How to connect packaged IP to a Zynq Processing System in IP Integrator. 

• Creating software applications to control the HDL IP using the generated C software drivers, and executing them on the ZedBoard.