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Signal integrity effects play a big part in the memory interface performance. Signal integrity simulations need to be performed for the memory interfaces, and the simu- lation recommendations need to be used for the PCB design as well as the memory controller options. For low-frequency interfaces the signal integrity has little effect on the signal and the interface can work reliably. At high frequencies the signal integrity effects like ringing, cross talk, ground bounce, and refl ections affect the signal quality and can result in data integrity problems. Impedance mismatch is one of the key aspects that needs to be taken care of in the memory interface design. Impedance mismatch causes signals to refl ect along the transmission line. The refl ections can subject the signals to ringing, overshoot, and undershoot which in turn will cause signals to be sampled improperly at the receiver. The source imped- ance must match with the trace impedance.
Figure 5.5 shows an example of a driver, transmission line, and receiver setup. The impedance of the driver, transmission line, and the receiver have to match to avoid impedance mismatch. Various termination schemes are available for you to match the impedance. You have the option of terminating on the PCB or use the on- chip termination that is available in the FPGA and in the memory device. Xilinx FPGAs have onboard programmable termination called Digitally Controlled Impedance ( DCI ). DCI offers on-chip termination for receivers and drivers across multiple confi gurations that will satisfy your system requirement. DCI helps you to leave the termination implementation to the FPGA and simplify the PCB design. Similar to the FPGAs , the memory devices also have on-chip termination called On Die Termination. On the FPGA end, various other options are provided to improve the signal integrity. Vivado provides attributes to control drive strength and slew rate. Drive strength and slew rate can be used to tune an interface for adequate speed while not overdriving the signals. The memory wizard tool in Vivado IP catalog will automatically chose the correct setting for a given memory interface. There are certain options like ODT that might have multiple choices. You have the choice to go with default or chose the option that matches your requirements.
Fig. 5.5 Driver, transmission line, and receiver example
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