Calibration

Calibration is a very important aspect of the memory controller design. The inter- face operates at very high data rates and due to that the data valid window will be very small. Good calibration techniques are required for reading and writing the data reliably for the memory interface. This section describes the concept of calibra- tion that would be applicable for all memory interfaces.

The data is captured from the memory and written to the memory at both the edges of the clock. A DDR4 operating at 3200 MT/s will have a clock period of 625 ps. With the dual data rate interface, the bit time would be 312 ps. Within the bit time, various uncertainties will affect the data valid window as shown in Fig. 5.1 .

The uncertainties shown in Fig. 5.1 will be a combination of variations from memory, FPGA , and PCB. The goal of calibration is to center the capture clock in the middle of data valid window during reads and have the write clock in the middle of the data valid window during writes. For read side the following would add to the uncertainties at a high level:

• Data valid time from the memory

• Any drift with respect to clock and data from memory that is sent to the FPGA

• Skew between different signals that pass through the PCB

• Board inter symbol interference

• Jitter on the clock that is fed to the memory

• Setup and hold requirements of the capture fl op in the FPGA

• Delay variations over voltage and temperature in elements used for calibration Write side would have the following added to the uncertainties at a high level:

• Duty cycle distortion and jitter on the clock that is fed to the memory

• Package skew and clock skew from the FPGA

• Delay variations over voltage and temperature in elements used for calibration

• Board inter symbol interference

• Setup and hold requirements from the memory device

Data bit time with uncertainties.png

Fig. 5.1 Data bit time with uncertainties

De-Skew Calibration

The read and write data from the memory can be skewed based on package skew, PCB skew, clock skew, internal routing skew, and variations in the delay elements used during calibration . For the parallel memory interfaces, the data to clock ratio varies from 4:1 to 36:1. In parallel memory interface where there is one clock per multiple data bits, the skew within the data bits will affect the effective data valid window. The skew in the interface will affect the effective data valid window as shown in Fig. 5.2 .

The function of the de-skew calibration would be to align all the data bits within the clock region so that the interface has the maximum data valid window for both read and write operation. The interface data valid window will be determined by the common time in which all the interfaces have valid data.

Read Calibration

The read clock at the output of the memory during read operations will not be center aligned with the data and will be edge aligned as shown in Fig. 5.3 .

Data bus with skew.png

Fig. 5.2 Data bus with skew

Read data and read clock.png

Fig. 5.3 Read data and read clock/strobe from memory

trobe after read calibration.png

Fig. 5.4 Read data and read clock/strobe after read calibration

The main function of the read calibration is to fi gure out the read valid window across all the associated data bits and center the capture clock in the middle of the data valid window. This stage will usually write a pattern to memory and read from it continuously. Write calibration might not have been completed before this stage. The writes to the memory has to be successful for this stage to function properly. Some memory standards have registers within the device that has predefi ned data patterns that can be used during this stage and would not require a write to the memory. For devices that do not have preloaded data pattern, the read calibration will write a simple data pattern. The simple data pattern will guarantee enough setup and hold margin to make sure the writes are successful. The calibration algorithms will start with the simple pattern or preloaded patterns to complete the initial stage. After the initial calibration, for higher data rate interfaces, a complex data pattern that mimics the worst case signal integrity effects will be used to further center the clock accurately in the data valid window.

Read calibration algorithm using the training pattern will scan the data eye to fi gure out the uncertainty region and the effective window in which data is valid. This stage requires multiple samples of the read data to accurately fi gure out the uncertainty region to account for jitter and other signal integrity effects. Once the scanning is done, the calibration algorithm will position the capture clock in the center of the eye as shown in Fig. 5.4 .

Read calibration in majority of the memory controller designs will include a stage for estimating the read latency. A read command will be issued by the memory controller, and it will reach the memory device after going through the delay in the address path. The memory device will have a spec for read latency, and the read data will appear on the read data bus after the read latency number of clock cycles from the time the read command was registered. The read data will have to go through the read data path delay and any other delay in the read capture stage. In most designs the read data will be captured using the clock/strobe from the memory and will be transferred to the controller clock domain for use in the other parts of the design. The memory interface will have multiple sets of data with its own read clock asso- ciated with it. All the data sets from the memory need not be aligned when it is available at the controller clock domain. Optional delay stages have to be added to align the entire interface when the data is available in the controller clock domain. The read valid calibration stage will estimate all the delays in clock cycles and provide the information on when the read data would be available at the controller clock domain after the read command is issued.

Write Calibration

The write calibration stage is required to center the write clock/strobe in the center of the write data. The memory devices have a requirement of having the write clock/ strobe to be in the center during write transactions. For high-speed interfaces in which every picosecond counts, a precise calibration would be required to center the clock/strobe in the write data window. The concept behind write calibration is very similar to read calibration. The calibration algorithm would write a data pattern into memory and read it back to see if the write was successful. During the write the write clock/strobe will be moved using fi ne resolution delays across the data bit time to fi gure out the optimal position.

Write calibration in most of the controllers will have write latency calibration. Similar to read latency calibration, this stage is to calibrate out the delays that are in the write path and estimate the write latency so that the controller can satisfy the write latency requirements for the memory device. Write calibration depending on the memory technology will have an additional calibration stage to align the write clock/strobe with the memory clock. The write clock/strobe will be a point to point connection. The memory clock will go to multiple components and will have more than one load. The arrival times of the write clock/strobe and the memory clock will not be aligned and this stage is to align them both.

VT Compensation

VT compensation is not necessarily a calibration stage but the logic to compensate for the voltage and temperature drift that will occur over the period of time. Initial calibration will calibrate out the process variations; the dynamic variations due to VT will need compensation. There can be difference in the way variations happen between the clock path and the data path. In the worst case scenario, the data path and the clock path can drift in opposite directions. The dynamic variations can happen at any rate. The VT compensation logic would have to sense the drift and correct for it.

The compensation logic would have to monitor the drift and compensate as and when the drift happens. If left uncorrected there will be reduction in margin and in certain conditions data corruption can occur due to too much variations. The com- pensation logic would have to monitor the FPGA conditions as well as the signals from memory to detect the movement. The compensation logic would need to mon- itor the read data and/or read clock/strobe coming from the memory. If the user traffi c does not have any read commands for a certain period of time, then the memory controller would issue read commands for maintenance purpose. The read data from these maintenance commands will not be passed on to the user interface. The interval between the maintenance commands is determined by the memory interface design requirements.

TABLE OF CONTENTS

De-Skew Calibration

Read Calibration

Write Calibration

VT Compensation