Interface Synthesis

(a) Launch the command prompt by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1 > Vivado HLS > Vivado HLS 2014.1 Command Prompt.

(b) Change the working directory to C:\Zynq_Book\HLS\tut3C. This folder contains the source and test files for a project, and also the Tcl script required to build the project, run_hls.tcl.

(c) Run the Tcl script using the command:

vivado_hls ‐f run_hls.tcl

(d) To open the project in the Vivado HLS GUI enter the following command:

vivado_hls ‐p matrix_mult_prj

And press Enter. This will open the Vivado HLS GUI for the project, which we will utilise in the next exercise.

(e) Open the source file matrix_mult.cpp from the Source section of the Explorer tab and click the C Synthesis button to synthesise the RTL design. When the synthesis report opens, scroll to the Interface section.

Note that the input arrays a and b, and the resultant product array prod have been implemented using the ap_memory protocol. This is inferred from the C++ source code, as the array type corresponds with the structure of memory.

Input arrays a and b are both 8 -bit signals on ports a_q0 and b_q0. The output array, prod is a 16-bit signal on port prod_d0. Each signal has a corresponding 5-bit address port, designated as a_address0, b_address0 and prod_address0.

The protocol also requires clock enable signals (a_ce0 and b_ce0), and a write enable (prod_we0).

Since the design requires more than one clock cycle to complete and is therefore synchronous, a clock and reset port have been synthesised as ap_clk and ap_rst, and both are 1-bit signals.

A block level control protocol with handshaking, ap_ctrl_hs, has also been implemented (ap_start, ap_done, ap_idle and ap_ready).

• The ap_start input is asserted, prompting block operation. This produces three output control signals indicating the stage of operation. • ap_ready indicates that the block is ready for new inputs. 

• ap_idle is an indication that data is currently processing data. 

• ap_done indicates that output data has been processed and is available.

Recalling Exercise 3B, the arrays were partitioned to reduce each into several smaller sections with expanded ports, control signals and implementation resources. This increased the bandwidth. This directly influenced the interface synthesis through use of directives.

This concludes this introduction to the design flow of Vivado HLS. This tool will be used further in future exercises, and synthesised RTL will be implemented as part of a larger functional model.