Getting Started

Xilinx memory solutions are part of Vivado IP catalog. You can generate various memory controller designs by selecting the IP cores available in the IP catalog. The following memory IPs are generally available for every generation of FPGAs :

• SDRAM : DDR3 and DDR4

• SRAM : QDRII + and QDRIV

• RLDRAM : RLDRAM -3

• LPDDR : LPDDR3 and LPDDR4

The variants for memory devices will vary for every generation of FPGAs based on the memory roadmap and availability. In this chapter only the memory that is prevalent will be discussed in detail. For example, in SDRAM the chapter will go into details for DDR4 . Most of the DDR4 concepts are applicable for DDR3 , LPDDR3 , and LPDDR4 .

Design Generation

Through the IP catalog in Vivado, you will be able to invoke the memory wizard tool for a given IP. The wizard will have multiple options to confi gure the IP. The options are split into "basic options” and “advanced options.” The basic options would be used to confi gure the following:

• Controller option : The memory controller is split into two parts: the physical layer and the controller. The controller converts the user commands into the par- ticular memory protocol commands. The controller will also have features built

in to improve the effi ciency. The physical layer is responsible for initializing the memory and performing calibration . The main function of calibration is to cap- ture read data reliably and to send write data with enough margin to the memory. Calibration is required to make sure the memory interface works reliably over a range of process voltage and temperature. You can choose to generate a design with memory controller and physical layer or just the physical layer. Usually a physical layer-only design is generated for use in cases in which a system requires a custom controller to be used with the physical layer. The physical layer-only option is usually only applicable to SDRAM designs which has com- plex controller functions.

• Clocking option : The memory controller frequency of operation will be chosen here. There will be an option to select the clock input to the memory controller.

• Memory device : You can choose the memory device as per your requirements. The menu will have multiple memory devices and confi gurations for you to choose from. If a particular memory type is not available, the tool provides options to generate a custom memory part for you. Other options like the data width, read and write latencies (if applicable), and burst length would be chosen here. For certain memory types, some pins like chip select or data mask are optional and that selection would be done here. Finally if applicable for certain memory types, the option to have ECC will also be provided here.

With the basic options described above, you can generate a memory controller that will satisfy your needs. You can use the advanced option to further customize the memory controller. The advanced options would vary by the memory controller type. In general there would be options to select the following:

• By default the controller is confi gured for effi ciency based on the default options. You can select switches that would improve effi ciency for your traffi c pattern.

• Provides advanced option for you to choose the input clock confi guration.

• Option to provide debug hooks and bring the status signals to the Vivado Labtools Hardware Manager for easy debug. All the memory controllers will come up with a status viewer from Vivado Labtools by default. The status viewer will display the calibration status, read/write margin, and other relevant information.

• Advanced options provided to speed up simulation with behavioral models.

• Option to generate additional clocks that is synchronous to the memory control- ler clock. The additional clocks would be useful for a system that needs to clock other blocks that are synchronous to the chosen memory controller.

• Options to enable other controller-specifi c advanced features. For example, self- refresh feature in DDR4 designs.

Pin Planning

The pin planning for the memory controller would be done in the main Vivado I/O Pin planner. To access the Vivado I/O planning environment, you would have to open the elaborated RTL design or the synthesized design. Once the design is opened, the I/O planning layout option can be chosen from the menu and pin selection can be done. A default pin out would be preloaded for the memory control- ler in the I/O planner. You can go with the default or choose your own custom pin out. In custom pin out, you have the option to do byte-level or pin- level selections. You can also read in an existing pin selection through the XDC fi le and use it for the IP pin out in I/O planner.

Example Design

The memory controller solutions have an example design associated with it. The example design can be invoked by right clicking on the generated IP in the Vivado console and choosing the option “Open IP Example Design.”

The example design (apart from the IP fi les that was generated) will have the necessary fi les for simulation and implementation. The example design is useful for you to get a quick start with implementation and simulation of the generated mem- ory controller. The example design can also be used as an instantiation template when you integrate the memory controller IP in your system. A traffi c generator that can send in different traffi c patterns depending upon your options will be part of the example design. The traffi c generator can generate patterns like PRBS23 that stresses the interface.

The implementation fl ow requires a top-level module that instantiates your design portion of the IP and the traffi c generator. This top-level fi le will be present in the example design. The example design will have all the required constraints for the implementation of the design. The example design can be taken through the implementation fl ow and a bit fi le can be generated. You can go through the I/O planner to customize the pin out of the example design as per your PCB layout. You can also skip the I/O planner and generate a bit fi le with the default pin out. You can use the example design to validate the memory interface in your PCB. Memory interfaces operates at a high data rate. During system bring up, the example design fl ow is a good way of bringing up the memory interface in the PCB in a unit level without the other parts of the system.

The behavioral simulation of example design can be performed by selecting the Run Simulation option in Vivado. The Vivado simulator is supported by default and the option to support various third-party simulators is provided. The simulation waveform will be opened in the Vivado GUI framework with the relevant signals that are important for the design. The example design will have a simulation top level that instantiates the user design, traffi c generator, memory model, clocking, and reset logic. The example design behavioral simulation provides you with the waveforms that show the interaction with the user interface and interaction of the memory interface signals with the controller and provides information on the laten- cies involved in the design.

TABLE OF CONTENTS

Design Generation

Pin Planning

Example Design