FONT SIZE : AAA
The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester ( IBERT ) core for FPGA transceivers is designed for evaluating and monitoring the transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic and access to ports and the dynamic reconfi guration port attributes of the transceivers. Communication logic is also included to allow the design to be run time accessible through JTAG .
The IBERT core provides a broad-based Physical Medium Attachment ( PMA ) evaluation and demonstration platform for FPGA transceivers. Parameterizable to use different transceivers and clocking topologies, the IBERT core can also be customized to use different line rates, reference clock rates, and logic widths. Data pattern generators and checkers are included for each GTX transceiver desired, giving several different pseudorandom binary sequences ( PRBS ) and clock patterns to be sent over the channels. In addition, the confi guration and tuning of the trans- ceivers are accessible through logic that communicates to the dynamic reconfi gura- tion port ( DRP ) of the GTX transceiver, in order to change attribute settings, as well as registers that control the values on the ports. At run time, the Vivado serial I/O analyzer communicates to the IBERT core through JTAG, using the Xilinx cables and proprietary logic that is part of the IBERT core.
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Embedded - CPLDs (Complex Programmable Logic Devices)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS:
Support
