Receiver

Each transceiver includes an independent receiver, made up of a PCS and a PMA . Figure 4.8 shows the blocks of the transceiver RX . High-speed serial data fl ows from traces on the board into the PMA of the transceiver RX , into the PCS , and fi nally into the FPGA logic.

RX transceiver block diagram.png

Fig. 4.8 RX transceiver block diagram

Some of the key elements within the transceiver RX are:

1. RX Analog front end

2. RX equalizer (DFE and LPM)

3. RX CDR

4. RX polarity control

5. RX pattern checker

6. RX Byte and Word Alignment

7. RX 8B/10B decoder

8. RX buffer bypass

9. RX elastic buffer

10. RX clock correction

11. RX channel bonding

12. RX gearbox

13. FPGA RX interface

RX Analog Front End

The RX analog front end ( AFE ) is a high-speed current-mode input differential buf- fer. It has these features:

• Confi gurable RX termination voltage

• Calibrated termination resistors

RX Equalizer (DFE and LPM)

A serial link bit error rate ( BER ) performance is a function of the transmitter, the transmission media, and the receiver. The transmission media or channel is bandwidth limited and the signal traveling through it is subjected to attenuation and distortion.

LPM mode ( left ) and DFE mode ( right ) block diagram.png

Fig. 4.9 LPM mode ( left ) and DFE mode ( right ) block diagram

There are two types of adaptive fi ltering available to the receiver depending on system level trade-offs between power and performance. Optimized for power with lower channel loss, the receiver has a power-effi cient adaptive mode named the low- power mode ( LPM ), see Fig. 4.9 .

For equalizing lossy channels, the DFE mode is available. See Fig. 4.9 for the transceiver. The DFE allows better compensation of transmission channel losses by providing a closer adjustment of fi lter parameters than when using a linear equalizer. However, a DFE cannot remove the precursor of a transmitted bit; it only compensates for the post-cursors. A linear equalizer allows precursor and post- cursor gain. The DFE mode is a discrete time-adaptive high-pass fi lter. The TAP values of the DFE are the coeffi cients of this fi lter that are set by the adaptive algorithm.

LPM mode is recommended for applications with line rates up to 11.2 Gb/s for short reach applications, with channel losses of 12 dB or less at the Nyquist fre- quency. DFE mode is recommended for medium to long-reach applications, with channel losses of 8 dB and above at the Nyquist frequency. A DFE has the advan- tage of equalizing a channel without amplifying noise and crosstalk. DFE can also correct refl ections caused by channel discontinuities within the fi rst fi ve post- cursors in transceivers. DFE mode is the best choice when crosstalk is a concern or when refl ections are identifi ed in a single-bit response analysis.

Both LPM and DFE modes must be carefully considered in 8B/10B applications or where data scrambling is not employed. To properly adapt to data, the auto adapta- tion in both LPM and DFE modes requires incoming data to be random. Patterns with characteristics similar to PRBS7 (or higher polynomial) are suffi ciently random for auto adaptation to properly choose the correct equalization setting.

RX CDR

The RX clock data recovery ( CDR ) circuit in each transceiver extracts the recovered clock and data from an incoming data stream. The transceiver employs phase rotator CDR architecture. Incoming data fi rst goes through receiver equalization stages. The equalized data is captured by an edge and a data sampler. The data captured by the data sampler is fed to the CDR state machine and the downstream transceiver blocks.

The CDR state machine uses the data from both the edge and data samplers to determine the phase of the incoming data stream and to control the phase interpolators (PIs). The phase for the edge sampler is locked to the transition region of the data stream, while the phase of the data sampler is positioned in the middle of the data eye.

The PLLs provides a base clock to the phase interpolator. The phase interpolator in turn produces fi ne, evenly spaced sampling phases to allow the CDR state machine to have fi ne phase control. The CDR state machine can track incoming data streams that can have a frequency offset from the local PLL reference clock.

RX Polarity Control

Similar to Tx Polarity Control (explained in Sect. 4.6.7 ), RXPLOLARITY (active High ) input can be used to swap the RXP and RXN differential pins.

RX Pattern Checker

The receiver includes a built-in PRBS checker. This checker can be set to check for one of four industry-standard PRBS patterns. The checker is self-synchronizing and works on the incoming data before comma alignment or decoding. This function can be used to test the signal integrity of the channel.

RX Byte and Word Alignment

Serial data must be aligned to symbol boundaries before it can be used as parallel data. To make alignment possible, transmitters send a recognizable sequence, usu- ally called a comma . The receiver searches for the comma in the incoming data. When it fi nds a comma , it moves the comma to a byte boundary so the received parallel words match the transmitted parallel words.

RX 8B/10B Decoder

If RX received data is 8B/10B encoded, it must be decoded. The transceiver has a built-in 8B/10B encoder in the TX and an 8B/10B decoder in the RX. The RX 8B/10B decoder has these features:

• Supports 2-byte, 4-byte, and 8-byte datapath operation

• Provides daisy-chained hookup of running disparity for proper disparity

• Generates K characters and status outputs

• Can be bypassed if incoming data is not 8 B/10 B encoded

• Pipes out 10-bit literal encoded values when encountering a not-in-table error

RX Buffer Bypass

Bypassing the RX elastic buffer is an advanced feature of the transceiver. The RX phase alignment circuit is used to adjust the phase difference between the PMA paral- lel clock domain ( XCLK ) and the RXUSRCLK domain when the RX elastic buffer is bypassed. It also performs the RX delay alignment by adjusting the RXUSRCLK to compensate for the temperature and voltage variations. Figure 4.10 shows the XCLK and RXUSRCLK domains, and Table 4.3 shows trade-offs between buffering and

RX phase alignment.png

Fig. 4.10 RX phase alignment

Table 4.3 RX buffer vs phase alignment

	RX elastic buffer	RX phase alignment
Ease of use	The RX buffer is the recommended default to use when possible. It is robust and easier to operat	Phase alignment is an advanced feature that requires extra logic and additional constraints on clock sources
Clocking options	Can use RX recovered clock or local clock (with clock correction)	Must use the RX recovered clock
Initialization	Works immediately	Must wait for all clocks to stabilize before performing the RX phase and delay alignment procedure
Latency	Buffer latency depends on features use, such as clock correction and channel bondin	Lower deterministic latency
Clock correction and channel bonding	Required for clock correction and channel bonding	Not performed inside the transceiver. Required to be implemented in user logic

phase alignment. The RX elastic buffer can be bypassed to reduce latency when the RX recovered clock is used to source RXUSRCLK and RXUSRCLK2 . When the RX elastic buffer is bypassed, latency through the RX datapath is low and deterministic, but clock correction and channel bonding are not available.

RX Elastic Buffer

The transceiver RX datapath has two internal parallel clock domains used in the PCS : the PMA parallel clock domain ( XCLK ) and the RXUSRCLK domain. To receive data, the PMA parallel rate must be suffi ciently close to the RXUSRCLK rate, and all phase differences between the two domains must be resolved.

RX Clock Correction

he RX elastic buffer is designed to bridge between two different clock domains, RXUSRCLK and XCLK , which is the recovered clock from CDR . Even if RXUSRCLK and XCLK are running at the same clock frequency, there is always a small frequency difference. Because XCLK and RXUSRCLK are not exactly the same, the difference can be accumulated to cause the RX elastic buffer to eventually overfl ow or under- flow unless it is corrected. To allow correction, each transceiver TX periodically transmits one or more special characters that the transceiver RX is allowed to remove or replicate in the RX elastic buffer as necessary. By removing characters when the RX elastic buffer is full and replicating characters when the RX elastic buffer is empty , the receiver can prevent overfl ow or underfl ow.

RX Channel Bonding

Protocols such as XAUI and PCI Express combine multiple serial transceiver connections to create a single higher throughput channel. Each serial transceiver connection is called one lane. Unless each of the serial connections is exactly the same length, skew between the lanes can cause data to be transmitted at the same time but arrive at different times. Channel bonding cancels out the skew between transceiver lanes by using the RX elastic buffer as a variable latency block. Channel bonding is also called channel deskew or lane-to-lane deskew . Transmitters used for a bonded channel all transmit a channel bonding character (or a sequence of characters) simultaneously. When the sequence is received, the receiver can determine the skew between lanes and adjust the latency of RX elastic buffers so that data is presented without skew at the RX fabric user interface.

RX Gear Box

The RX gearbox provides support for 64B/66B and 64B/67B header and payload separation. The gearbox uses output pins RXDATA [63:0] and RXHEADER [2:0] for the payload and header of the received data in normal mode. RX gearbox operates with the PMA using a single clock. Because of this, occasionally, the output data is invalid. The data out of the RX gearbox is not necessarily aligned. Alignment is done in the FPGA logic. The RXGEARBOXSLIP port can be used to slip the data from the gearbox cycle by cycle until correct alignment is reached. It takes a specifi c number of cycles before the bitslip operation is processed and the output data is stable. Descrambling of the data and block synchronization is done in the FPGA logic.

The RX gearbox operates the same in either external sequence counter mode or internal sequence counter mode.

FPGA RX Interface

The FPGA RX interface is the FPGA’s gateway to the RX datapath of the transceiver. Applications transmit data through the transceiver by writing data to the RXDATA port. The width of the port can be confi gured to be two, four, or eight bytes wide. The rate of the parallel clock at the interface is determined by the RX line rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled.

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