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Home > FPGA Technical Tutorials > Programming FPGAs Getting Started with Verilog > Timer Example > State Machine Design

State Machine Design

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To allow this example to work on all three example boards, it will use three  seven-segment digits (the Elbert 2 has only three digits). Two digits display  seconds, and one displays minutes. The “Up/Down” push buttons will set the  minutes, a “Start/Stop” button will begin countdown timing, and a “Cancel” button will reset the timer to the number of minutes last used. A buzzer will be wired  up to the board to make a noise when the countdown reaches zero. The state  machine for this project is shown in Figure 6-2.

The initial state is SETTING, and while in this state, the “Up” and “Down” buttons will add or take away 1 from the digit being displayed in the minutes digit.  Once the “Start/Stop” button is pressed, the project moves to the RUNNING state.  Pressing “Start/Stop” will immediately take you back to the SETTING state, as will  pressing “Cancel.” However, pressing “Cancel” will also reset the time. While in 

State machine for the timerpng

the SETTING state, every second, the time displayed will be decreased by 1 second  until the countdown reaches 000, at which point the BEEPING state is entered. The BEEPING state sounds the buzzer until the “Cancel” button is pressed, at  which point the system returns to the SETTING state, and the time is reset, ready  to use the timer again.

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