FONT SIZE : AAA
Each transceiver includes an independent transmitter, which consists of a PCS and a PMA . Figure 4.6 shows the functional blocks of the transmitter. Parallel data flows from the FPGA logic into the FPGA TX interface, through the PCS and PMA , and then out of the TX driver as high-speed serial data.
Some of the key elements within the GTX / GTH transceiver TX are:
1. FPGA TX interface
2. TX 8B/10B encoder
3. TX gearbox
4. TX buffer
5. TX buffer bypass
6. TX pattern generator
7. TX polarity control
8. TX confi gurable driver
The FPGA TX interface is the FPGA’s gateway to the TX datapath of the trans- ceiver. Applications transmit data through the transceiver by writing data to the TXDATA port. The width of the port can be confi gured to be two, four, or eight bytes wide. The FPGA TX interface includes parallel clocks used in PCS logic. The parallel clock rate depends on the internal datawidth and the TX line rate.
Many protocols use 8B/10B encoding on outgoing data. 8B/10B is an industry- standard encoding scheme that trades two bits overhead per byte for achieved DC balance and bounded disparity to allow reasonable clock recovery. The trans- ceiver has a built-in 8B/10B TX path to encode TX data without consuming FPGA resources. Enabling the 8B/10B encoder increases latency through the TX path. The 8B/10B encoder can be disabled or bypassed to minimize latency, if not needed.
Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10B encoding while retaining the benefi ts of an encoding scheme. The TX gearbox provides support for 64B/66B and 64B/67B header and payload combin- ing. The TX gearbox has two operating modes. The external sequence counter oper- ating mode must be implemented in user logic. The second mode uses an internal sequence counter. Due to additional functionality, latency through the gearbox block is expected to be longer.
Fig. 4.7 TX clock domains
Table 4.2 TX buffer vs phase alignment
The transceiver TX datapath has two internal parallel clock domains used in the PCS : the PMA parallel clock domain ( XCLK ) and the TXUSRCLK domain. To transmit data, the XCLK rate must match the TXUSRCLK rate, and all phase differences between the two domains must be resolved. Figure 4.7 shows the XCLK and TXUSRCLK domains.
The transmitter includes a TX buffer and a TX phase alignment circuit to resolve phase differences between the XCLK and TXUSRCLK domains. The TX phase alignment circuit is used when TX buffer is bypassed. All TX datapaths must use either the TX buffer or the TX phase alignment circuit. Table 4.2 shows the trade-off between buffering and phase alignment.
Bypassing the TX buffer is an advanced feature of the transceiver. The TX phase align- ment circuit is used to adjust the phase difference between the PMA parallel clock domain ( XCLK ) and the TXUSRCLK domain when the TX buffer is bypassed. It also performs the TX delay alignment by adjusting the TXUSRCLK to compensate for the temperature and voltage variations. The combined TX phase and delay alignments can be automatically performed by the transceiver or manually controlled by the user.
Pseudorandom bit sequences ( PRBS ) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specifi c properties that can be used to measure the quality of a link. The error insertion function is sup- ported to verify link connection and also for jitter tolerance tests. When an inverted PRBS pattern is necessary, TXPOLARITY signal is used to control polarity.
If TXP and TXN differential traces are accidentally swapped on the PCB, the differ- ential data transmitted by the transceiver TX is reversed. One solution is to invert the parallel data before serialization and transmission to offset the reversed polarity on the differential pair. The TX polarity control can be accessed through the TXPOLARITY input from the fabric user interface.
The transceiver TX driver is a high-speed current-mode differential output buffer.
To maximize signal integrity, it includes these features:
• Differential voltage control
• Precursor and post-cursor transmit preemphasis
• Calibrated termination resistors
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Embedded - CPLDs (Complex Programmable Logic Devices)
Lifecycle:Active Active
RoHS:
Support
